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there is no standardized connector in common use though intel defines one for use for debug modules 3 a small number of lpc peripheral daughterboards are available with pinouts proprietary to the motherboard vendor trusted platform modules tpms 2 post cards for displaying bios diagnostic codes 4 and isa compatible serial port peripherals for industrial use 5 device discovery is not supported since only motherboard devices or specific models of tpm are connected the host firmware bios uefi image will include a static description of any devices and their i o addresses expected to be present on a particular motherboard signals edit lpc control signals are active low as indicated by the symbol in their names signals are divided into three categories unidirectional these are driven from a single source at all times open collector these are low speed signals which are pulled up to the inactive state by the host when not in use and may be pulled down by any device bidirectional these high speed signals are actively driven high for one cycle whenever a device is done using them after which weak pull up resistors hold them high until another device begins using them the lpc specification defines seven mandatory signals required for bidirectional data transfer lclk unidirectional from host 33 3 mhz clock may be connected to the conventional pci clock pciclk thereby not requiring a dedicated pin on the host south bridge like pci other signals are driven after the falling edge of lclk and received after the rising edge lreset open collector active low bus reset may be connected to pcirst lframe unidirectional from host this active low signal indicates the beginning of an lpc bus transaction only the host may initiate bus transactions lad 3 0 bidirectional these four bidirectional signals carry multiplexed address data and other information there are six additional signals defined which are optional for lpc devices that do not require their functionality but support for the first two is mandatory for the host ldrq unidirectional from device dma bus master request this is an output from a device that wants to perform direct memory access either via the intel 8237 compatible dma controller or the lpc specific bus master protocol the host must provide one corresponding input pin per device that needs it minimum two serirq bidirectional serialized intel 8259 compatible interrupt signal 6 one line is shared by all lpc devices and the host like the lad lines this has a weak pull up which will maintain it high if no device is driving it clkrun open collector signal used to restart the clock in systems that can stop it for power management not required if the host does not stop the clock may be connected to the equivalent pci signal lpme open collector power management event to wake the system from a sleep state equivalent to the pci bus pme signal lsmi open collector system management interrupt request this is only required if an lpc device needs to trigger an smi in response to a bus access e g to perform software emulation of a missing hardware peripheral otherwise the slower serirq protocol can be used to request an smi lpcpd unidirectional from host optional output from the host to warn the lpc device that power is about to be removed and it should not make any interrupt or dma requests timing and performance edit the lpc bus derives its electrical conventions from those of conventional pci in particular it shares the restriction that two idle cycles are required to turn around any bus signal so that a different device is speaking in the first the bus is actively driven high in the second the bus is undriven and held high by the pull up resistors a new device may begin sending data over the bus on the third cycle lpc operations spend a large fraction of their time performing such turn arounds as mentioned the lpc bus is designed to have performance similar to the isa bus the exact data transfer rates depend on the type of bus access i o memory dma firmware performed and by the speed of the host and the lpc device all bus cycles spend a majority of their time in overhead rather than data transfer except the 16 and 128 byte firmware read cycles which have 17 cycles of overhead but 32 and 256 cycles respectively of data transfer achieving throughputs of 10 88 and 15 63 mb s 7 the next fastest bus cycle defined in the standard the 32 bit isa style dma write cycle spends only 8 of 20 total clock cycles transferring data the other 12 cycles are overhead achieving up to 6 67 mb s 7 one of the slowest bus cycles is a simple memory read or write where only 2 of the 17 clock cycles plus any wait states imposed by the device transfer data for a transfer rate of 1 96 mb s transaction structure edit lpc transactions begin on a low to high transition of lframe while lframe is low the host places a 4 bit start code on the lad lines the code sent on the last cycle before lframe transitions high defines the following bus transaction normally the host only holds lframe low for a single clock cycle for efficiency an exception is the abort transaction which may begin even in the middle of another operation the host pulls lframe low for a minimum of four clock cycles during which any devices must cease to drive the lad bus on the fourth cycle the host drives lad high to 1111 upon the high to low transition of lframe the bus is reset to an idle state in almost all other cases lpc transactions use the following general structure start code transaction type and address from host data from host if a write bus turnaround 2 cycles sync from device 1 or more cycles data from device if a read bus turnaround 2 cycles dma transfers differ somewhat isa compatible dma may have multiple sync and data phases bus master dma has a bus turnaround immediately following the start code and no final turnaround the sync phase allows the device to insert wait states in the transaction there are six possible sync values all with even parity even hamming weight three of them end the sync phase while the other three cause the host to wait for another sync nibble 0000 ready the device is ready to proceed with the transaction for dma cycles this also clears the dma request dreq signal 0011 not used 0101 short wait another sync cycle follows at most 8 short wait cycles are permitted 0110 long wait like short wait but the wait may be long e g enhanced parallel port operations 1001 ready more a dma only code that signals ready and the device requests additional dma cycles dreq remains asserted 1010 error the device is ready to proceed but there was some serious error such as a parity error with the transfer this is equivalent to the isa bus iochk or pci bus serr signals in the case of a read data follows but is likely to be corrupted 1100 not used 1111 device not present if no device responds to the transaction the host will see this code and can abort the transaction to accommodate slow devices up to 2 cycles of this code are permitted before the transaction is aborted applications edit intel designed the lpc bus so that the system bios image could be stored in a single flash memory chip directly connected to the lpc bus intel also made it possible to put operating system images and software applications on a single flash memory chip directly connected to the lpc bus as an alternative to a parallel ata port 8 a cpld or fpga can implement an lpc host or peripheral 9 the original xbox game console has an lpc debug port that can be used to force the xbox to boot new code 10 11 isa compatible operation edit all isa compatible lpc bus transactions use start code of 0000 7 during the first cycle with lframe high again the host drives a cycle type direction ctdir field two bits indicating the type i o memory or dma and one bit indicating the direction read from device or write to device of the transfer to follow this is followed by the transfer address field whose size depends on the type of cycle for i o access the address is 16 bits transferred most significant nibble first over 4 cycles for system memory access the address is 32 bits transferred most significant nibble first over 8 cycles for isa compatible dma accesses there is no address per se but a two clock cycles transfer a nibble containing the dma channel number and a second nibble giving the transfer size the memory address is programmed into the isa style dma controller in the chipset or the cpu outside of the lpc bus see isa compatible dma below isa compatible reads and writes edit memory and i o accesses are allowed as single byte accesses only and operate as described in transaction structure address data from host if write turnaround sync data from device if read if the host attempts a transfer to an unused address no device will drive the sync cycles and the host will see 1111 on the lad bus after seeing three cycles of 1111 two cycles are allowed in addition to the two turn around cycles for a slow device to decode the address and begin driving sync patterns the host will abort the operation isa compatible dma edit the platform controller hub pch chip or the southbridge chip acts as the host and controls the lpc bus it also acts as the central dma controller for devices on that bus if the memory controller is in the chipset in cpus that contain their own memory controller s the dma controller is located in the cpu for compatibility with software originally written for systems with the isa bus the dma controller contains the circuit equivalents of legacy onboard peripherals of the ibm pc at architecture such as the two programmable interrupt controllers the programmable interval timer and two isa dma controllers which are all involved in isa style dma isa compatible dma uses an intel 8237 compatible dma controller on the host which keeps track of the location and length of the memory buffer as well as the direction of the transfer the device simply requests service from a given dma channel number and the host performs a dma access on the lpc bus the request is made by a virtual isa compatible dma request drq line which is emulated using the device s ldrq signal to indicate transitions on the emulated drq line this is done with 6 bit requests on the ldrq signal a 0 start bit the 3 bit dma channel number most significant bit first one bit of new request level almost always 1 indicating that a dma transfer is requested and a final 1 stop bit the host responds by performing a dma cycle at the next available opportunity dma cycles are named based on the direction of memory access so a read is a transfer to the lpc device and a write is a transfer from the lpc device the address consists of 6 bits sent as two nibbles a 3 bit channel number and 1 bit terminal count indication the isa bus s tc pin or the 8237 s eop output followed by a 2 bit transfer size by default dma channels 0 3 perform 8 bit transfers and channels 5 7 perform 16 bit transfers but an lpc specific extension allows 1 2 or 4 byte transfers on any channel when a multi byte transfer is performed each byte has its own sync field as described below a normal sync ready pattern of 0000 or an error pattern of 1010 also causes a deassertion of the corresponding emulated dma request signal the host will stop dma after the immediately following byte until the device makes another dma request via the ldrq signal a sync pattern of 1001 indicates that the host should consider he device s dma request still active the host will continue with any remaining bytes in this transfer or start another transfer as appropriate without a separate request via ldrq for a dma write where data is transferred from the device the sync field is followed by the 8 bits of data and another sync field until the host specified length for this transfer is reached or the device stops the transfer a two cycle turnaround field completes the transaction for a dma read where data is transferred to the device the sync field is followed by a turnaround and the data turnaround sync turnaround sequence repeats for each byte transferred serialized interrupts edit interrupts are transmitted over a single shared serirq line using the serialized interrupts for pci protocol originally developed for the pci bus 6 the host periodically sends interrupt packets within which each interrupt request is assigned a 1 clock time slot separated by 2 clock turnaround cycles the initial synchronization is done by the host as a simplified example the host drives the serirq line low for four to eight clocks followed by a 2 clock turnaround cycle serirq is driven high for 1 clock then floats high for the second turnaround clock if a device needs to request irq 6 it waits for 6 3 18 clocks then drives serirq low for one clock and high for another the devices can recognize the beginning of the frame because only the host will ever drive the line low for more than one cycle the host identifies the interrupt by counting the number of clocks cycles if it sees the serirq line driven low at the eighteenth clock then irq 18 3 6 is asserted the number of interrupt slots is system specific with 17 being a typical number 16 isa compatible interrupts irq0 irq15 plus nmi after the final interrupt slot the host appends a stop signal consisting of two or three low cycles followed by two turnaround cycles in continuous mode the host periodically initiates a new packet there is also a quiet mode in which a device requests a new packet by driving serirq low for one clock cycle the host then continues driving the line low for the other seven clocks from this point on the protocol is the same the mode is controlled by the length of the host s stop signal at the end of each packet if it consists of three clocks of low signal continuous mode follows and only the host may begin a new packet if the stop signal consists of two low clocks quiet mode follows and any device may initiate an interrupt packet lpc non isa transactions edit start field values other than 0000 or 1111 are used to indicate various non isa compatible transfers 7 the supported transfers are start 1101 1110 firmware memory read and write edit this allows the firmware bios to be located outside the usual peripheral address space these transfers are similar to isa compatible transfers except that there is no ctdir field the direction is encoded in the start field 1101 for read 1110 for write the first 4 address bits are defined as a device select idsel field to allow the selection of one firmware hub out of many for example a second firmware hub can be used to hold a backup bios in case the primary bios is corrupted by malware or a bad flash the remaining 28 address bits define the address within the device most significant nibble first the address is followed by a size field supported read write sizes are 1 2 and 4 bytes sizes of 16 and 128 bytes are supported for read only the data is transferred in one continuous burst with no wait states there is only one sync field for the w...
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