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parallel ram wikipedia jump to content main menu main menu move to sidebar hide navigation main page contents current events random article about wikipedia contact us contribute help learn to edit community portal recent changes upload file special pages search search appearance donate create account log in personal tools donate create account log in contents move to sidebar hide top 1 read write conflicts 2 implementation 3 example code 4 see also 5 references 6 external links toggle the table of contents parallel ram 10 languages deutsch فارسی français 日本語 한국어 norsk bokmål português română українська 中文 edit links article talk english read edit view history tools tools move to sidebar hide actions read edit view history general what links here related changes upload file permanent link page information cite this page get shortened url switch to legacy parser print export download as pdf printable version in other projects wikidata item appearance move to sidebar hide from wikipedia the free encyclopedia abstract computer for designing parallel algorithms this article includes a list of general references but lacks sufficient corresponding inline citations please help improve this article by introducing more precise citations july 2016 learn how and when to remove this message in computer science a parallel random access machine parallel ram or pram is a shared memory abstract machine as its name indicates the pram is intended as the parallel computing analogy to the random access machine ram not to be confused with random access memory 1 in the same way that the ram is used by sequential algorithm designers to model algorithmic performance such as time complexity the pram is used by parallel algorithm designers to model parallel algorithmic performance such as time complexity where the number of processors assumed is typically also stated similar to the way in which the ram model neglects practical issues such as access time to cache memory versus main memory the pram model neglects such issues as synchronization and communication but provides any problem size dependent number of processors algorithm cost for instance is estimated using two parameters o time and o time processor_number read write conflicts edit read write conflicts commonly termed interlocking in accessing the same shared memory location simultaneously are resolved by one of the following strategies exclusive read exclusive write erew every memory cell can be read or written to by only one processor at a time concurrent read exclusive write crew multiple processors can read a memory cell but only one can write at a time exclusive read concurrent write ercw mostly never considered because it mostly doesn t add more power 2 concurrent read concurrent write crcw multiple processors can read and write a crcw pram is sometimes called a concurrent random access machine 3 here e and c stand for exclusive and concurrent respectively the read causes no discrepancies while the concurrent write is further defined as common all processors write the same value otherwise is illegal arbitrary only one arbitrary attempt is successful others retire priority processor rank indicates who gets to write another kind of array reduction operation like sum logical and or max several simplifying assumptions are made while considering the development of algorithms for pram they are there is no limit on the number of processors in the machine any memory location is uniformly accessible from any processor there is no limit on the amount of shared memory in the system resource contention is absent the programs written on these machines are in general of type simd these kinds of algorithms are useful for understanding the exploitation of concurrency dividing the original problem into similar sub problems and solving them in parallel the introduction of the formal p ram model in wyllie s 1979 thesis 4 had the aim of quantifying analysis of parallel algorithms in a way analogous to the turing machine the analysis focused on a mimd model of programming using a crew model but showed that many variants including implementing a crcw model and implementing on an simd machine were possible with only constant overhead implementation edit pram algorithms cannot be parallelized with the combination of cpu and dynamic random access memory dram because dram does not allow concurrent access to a single bank not even different addresses in the bank but they can be implemented in hardware or read write to the internal static random access memory sram blocks of a field programmable gate array fpga it can be done using a crcw algorithm however the test for practical relevance of pram or ram algorithms depends on whether their cost model provides an effective abstraction of some computer the structure of that computer can be quite different than the abstract model the knowledge of the layers of software and hardware that need to be inserted is beyond the scope of this article but articles such as vishkin 2011 demonstrate how a pram like abstraction can be supported by the explicit multi threading xmt paradigm and articles such as caragea vishkin 2011 demonstrate that a pram algorithm for the maximum flow problem can provide strong speedups relative to the fastest serial program for the same problem the article ghanim vishkin barua 2018 demonstrated that pram algorithms as is can achieve competitive performance even without any additional effort to cast them as multi threaded programs on xmt example code edit this is an example of systemverilog code which finds the maximum value in the array in only 2 clock cycles it compares all the combinations of the elements in the array at the first clock and merges the result at the second clock it uses crcw memory m i 1 and maxno data i are written concurrently the concurrency causes no conflicts because the algorithm guarantees that the same value is written to the same memory this code can be run on fpga hardware module findmax parameter int len 8 input bit clock resetn input bit 7 0 data len output bit 7 0 maxno typedef enum bit 1 0 compare merge done state state state bit m len int i j always_ff posedge clock negedge resetn begin if resetn begin for i 0 i len i m i 0 state compare end else begin case state compare begin for i 0 i len i begin for j 0 j len j begin if data i data j m i 1 end end state merge end merge begin for i 0 i len i begin if m i 0 maxno data i end state done end endcase end end endmodule see also edit analysis of pram algorithms flynn s taxonomy lock free and wait free algorithms random access machine parallel programming model xmtc parallel external memory model references edit fortune steven wyllie james 1978 05 01 parallelism in random access machines proceedings of the tenth annual acm symposium on theory of computing stoc 78 new york ny usa association for computing machinery pp 114 118 doi 10 1145 800133 804339 hdl 1813 7454 isbn 978 1 4503 7437 8 mackenzie philip d ramachandran vijaya 1998 04 06 ercw prams and optical communication theoretical computer science 196 1 153 180 doi 10 1016 s0304 3975 97 00199 0 issn 0304 3975 neil immerman expressibility and parallel complexity siam journal on computing vol 18 no 3 pp 625 638 1989 wyllie james c the complexity of parallel computations phd thesis dept of computer science cornell university eppstein david galil zvi 1988 parallel algorithmic techniques for combinatorial computation annu rev comput sci 3 233 283 doi 10 1146 annurev cs 03 060188 001313 jaja joseph 1992 an introduction to parallel algorithms addison wesley isbn 0 201 54856 9 karp richard m ramachandran vijaya 1988 a survey of parallel algorithms for shared memory machines university of california berkeley department of eecs tech rep ucb csd 88 408 keller jörg christoph keßler jesper träff 2001 practical pram programming john wiley and sons isbn 0 471 35351 5 vishkin uzi 2009 thinking in parallel some basic data parallel algorithms and techniques 104 pages pdf class notes of courses on parallel algorithms taught since 1992 at the university of maryland college park tel aviv university and the technion vishkin uzi 2011 using simple abstraction to reinvent computing for parallelism communications of the acm 54 75 85 doi 10 1145 1866739 1866757 caragea george constantin vishkin uzi 2011 brief announcement better speedups for parallel max flow proceedings of the 23rd acm symposium on parallelism in algorithms and architectures spaa 11 p 131 doi 10 1145 1989493 1989511 isbn 9781450307437 s2cid 5511743 ghanim fady vishkin uzi barua rajeev 2018 easy pram based high performance parallel programming with ice ieee transactions on parallel and distributed systems 29 2 377 390 doi 10 1109 tpds 2017 2754376 hdl 1903 18521 external links edit saarland university s prototype pram archived 2016 03 03 at the wayback machine university of maryland s pram on chip prototype this prototype seeks to put many parallel processors and the fabric for inter connecting them on a single chip xmtc pram like programming software release v t e parallel computing general distributed computing parallel computing parallel algorithm massively parallel cloud computing high performance computing multiprocessing manycore processor gpgpu computer network systolic array levels bit instruction thread task data memory loop pipeline multithreading temporal simultaneous smt simultaneous and heterogenous speculative spmt preemptive cooperative clustered multi thread cmt hardware scout theory pram model pem model analysis of parallel algorithms amdahl s law gustafson s law cost efficiency karp flatt metric slowdown speedup elements process thread fiber instruction window array coordination multiprocessing memory coherence cache coherence cache invalidation barrier synchronization application checkpointing programming stream processing dataflow programming models implicit parallelism explicit parallelism concurrency non blocking algorithm hardware flynn s taxonomy sisd simd array processing simt pipelined processing associative processing misd mimd dataflow architecture pipelined processor superscalar processor vector processor multiprocessor symmetric asymmetric memory shared distributed distributed shared uma numa coma massively parallel computer computer cluster beowulf cluster grid computer hardware acceleration apis ateji px boost chapel hpx charm cilk coarray fortran cuda dryad c amp global arrays gpuopen mpi openmp opencl openhmpp openacc parallel extensions pvm pthreads raftlib rocm upc tbb zpl problems automatic parallelization cache stampede deadlock deterministic algorithm embarrassingly parallel parallel slowdown race condition software lockout scalability starvation category parallel computing authority control databases gnd retrieved from https en wikipedia org w index php title parallel_ram oldid 1305271883 categories models of computation analysis of parallel algorithms hidden categories articles with short description short description matches wikidata articles lacking in text citations from july 2016 all articles lacking in text citations webarchive template wayback links this page was last edited on 11 august 2025 at 02 40 utc page was rendered with parsoid text is available under the creative commons attribution sharealike 4 0 license additional terms may apply by using this site you agree to the terms of use and privacy policy wikipedia is a registered trademark of the wikimedia foundation inc a non profit organization privacy policy about wikipedia disclaimers contact wikipedia legal safety contacts code of conduct developers statistics cookie statement mobile view search search toggle the table of contents parallel ram 10 languages add topic
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