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opcode wikipedia jump to content main menu main menu move to sidebar hide navigation main page contents current events random article about wikipedia contact us contribute help learn to edit community portal recent changes upload file special pages search search appearance donate create account log in personal tools donate create account log in contents move to sidebar hide top 1 cpus toggle cpus subsection 1 1 sample opcode table 2 software instruction sets 3 see also 4 references toggle the table of contents opcode 26 languages العربية català čeština deutsch español فارسی français gaeilge magyar bahasa indonesia ido italiano 日本語 한국어 lombard nederlands polski português русский simple english српски srpski svenska türkçe українська 粵語 中文 edit links article talk english read edit view history tools tools move to sidebar hide actions read edit view history general what links here related changes upload file permanent link page information cite this page get shortened url switch to legacy parser print export download as pdf printable version in other projects wikidata item appearance move to sidebar hide from wikipedia the free encyclopedia part of a machine instruction machine code general concepts instruction set opcode illegal opcode opcode table opcode prefix operand addressing mode instructions nop branch indirect branch repeat instruction execute instruction bit manipulation instructions v t e in computing an opcode abbreviated from operation code 1 2 is an enumerated value that specifies the operation to be performed opcodes are employed in hardware devices such as arithmetic logic units alus central processing units cpus and software instruction sets in alus the opcode is directly applied to circuitry via an input signal bus in contrast in cpus the opcode is the portion of a machine language instruction that specifies the operation to be performed cpus edit opcodes are found in the machine language instructions of cpus as well as in some abstract computing machines in cpus an opcode may be referred to as an instruction machine code 3 instruction code 4 instruction syllable 5 6 7 8 instruction parcel or opstring 9 2 for any particular processor which may be a general cpu or a more specialized processing unit the opcodes are defined by the processor s instruction set architecture isa 10 they can be described using an opcode table the types of operations may include arithmetic data copying logical operations program control and special instructions e g cpuid 10 in addition to the opcode many instructions specify the data known as operands the operation will act upon although some instructions may have implicit operands or none 10 some instruction sets have nearly uniform fields for opcode and operand specifiers whereas others e g x86 architecture have a less uniform variable length structure 10 11 instruction sets can be extended through opcode prefixes which add a subset of new instructions made up of existing opcodes following reserved byte sequences 12 sample opcode table edit this table shows opcodes of a simple 8 bit microprocessor the intel 8008 from 1972 each opcode is 8 bits long each is shown as a binary pattern of ones and zeros in the opcode column up to two additional fields may be embedded into the opcode some 3 bit fields are labeled ddd sss cc and alu the sss source and ddd destination fields specify one of the eight possible 8008 registers or memory a b c d e h l or m cc specifies one of eight result conditions that will activate certain jmp cal and ret instructions alu specifies one of a possible eight arithmetic logic unit functions to be performed during an instruction specifically add add with carry subtract subtract with borrow logical and logical xor logical or and compare the x in some fields means that either a 1 or 0 can be inserted with no effect the fixed ones and zeros are combined with the parameter fields to build the 8 bit opcode additionally the full instruction might require one or two additional bytes of operands these are shown in the second major column of the table labeled operands if no operands are required the column is filled with a dash since the ones and zeros are difficult to remember the mnemonic column shows a short easy to remember letter code that an assembly language programmer may use to invoke the required opcode the description column shows the function performed by the microprocessor when it encounters a specific opcode opcode operands mnemonic description 7 6 5 4 3 2 1 0 b2 b3 0 0 0 0 0 0 0 x hlt halt 0 0 ddd 0 0 0 inr ddd ddd 1 except a and m 0 0 ddd 0 0 1 dcr ddd ddd 1 except a and m 0 0 0 0 0 0 1 0 rlc a 1 7 a 0 6 a 0 cy a 7 0 0 cc 0 1 1 rcc ret conditional if cc true p stack 0 0 alu 1 0 0 data adi aci sui sbi ndi xri ori cpi data a a alu operation data 0 0 n 1 0 1 rst n stack p p n x 8 0 0 ddd 1 1 0 data lri data load r with immediate data ddd data 0 0 x x x 1 1 1 ret p stack 0 0 0 0 1 0 1 0 rrc a 0 6 a 1 7 a 7 cy a 0 0 0 0 1 0 0 1 0 ral a 1 7 a 0 6 cy a 7 a 0 cy 0 0 0 1 1 0 1 0 rar a 0 6 a 1 7 cy a 0 a 7 cy 0 1 cc 0 0 0 addlo addhi jcc add jmp conditional if cc true p add 0 1 0 0 port 1 inp port a port ports 0 7 only 0 1 port 1 out port port a ports 8 31 only 0 1 cc 0 1 0 addlo addhi ccc add cal conditional if cc true stack p p add 0 1 x x x 1 0 0 addlo addhi jmp add p add 0 1 x x x 1 1 0 addlo addhi cal add stack p p add 1 0 alu sss adr acr sur sbr ndr xrr orr cpr a a alu operation sss 1 1 ddd sss lds load d with s ddd sss 1 1 1 1 1 1 1 1 hlt halt 7 6 5 4 3 2 1 0 b2 b3 mnemonic description sss ddd 2 1 0 cc alu a 0 0 0 fc c false adr adi a a arg b 0 0 1 fz z false acr aci a a arg cy c 0 1 0 fs s false sur sui a a arg d 0 1 1 fp p odd sbr sbi a a arg cy e 1 0 0 tc c true ndr ndi a a arg h 1 0 1 tz z true xrr xri a a arg l 1 1 0 ts s true orr ori a a arg m 1 1 1 tp p even cpr cpi a arg sss ddd 2 1 0 cc alu software instruction sets edit opcodes can be found in bytecodes and other representations intended for execution by software interpreters these often employ slightly higher level data types and operations than those found in hardware opcodes but are nevertheless constructed along similar lines examples include the byte code found in java class files which are interpreted by java virtual machines the byte code used in gnu emacs for compiled lisp code and net common intermediate language 13 see also edit computer programming portal gadget machine instruction sequence illegal opcode syllable computing fused operation references edit barron david william 1978 1971 1969 2 1 symbolic instructions written at university of southampton southampton uk in floretin j john ed assemblers and loaders computer monographs 3 ed new york usa elsevier north holland inc p 7 isbn 0 444 19462 2 lccn 78 19961 xii 100 pages 1 2 chiba shigeru 2007 1999 javassist a java bytecode translator toolkit archived from the original on 2020 03 02 retrieved 2016 05 27 appendix b instruction machine codes pdf mcs 4 assembly language programming manual the intellec 4 microcomputer system programming manual preliminary ed santa clara california usa intel corporation december 1973 pp b 1 b 8 mcs 030 1273 1 archived pdf from the original on 2020 03 01 retrieved 2020 03 02 raphael howard a ed november 1974 the functions of a computer instruction register and decoder pdf mcs 40 user s manual for logic designers santa clara california usa intel corporation p viii archived pdf from the original on 2020 03 03 retrieved 2020 03 03 each operation that the processor can perform is identified by a unique binary number known as an instruction code jones douglas w june 1988 a minimal cisc acm sigarch computer architecture news 16 3 new york usa association for computing machinery acm 56 63 doi 10 1145 48675 48684 s2cid 17280173 domagała łukasz 2012 7 1 4 benchmark suite application of clp to instruction modulo scheduling for vliw processors gliwice poland jacek skalmierski computer studio pp 80 83 83 isbn 978 83 62652 42 6 archived from the original on 2020 03 02 retrieved 2016 05 28 smotherman mark 2016 2013 multiple instruction issue school of computing clemson university archived from the original on 2016 05 28 retrieved 2016 05 28 jones douglas w 2016 2012 a minimal cisc computer architecture on line collection iowa city usa the university of iowa department of computer science archived from the original on 2020 03 02 retrieved 2016 05 28 schulman andrew 2005 07 01 finding binary clones with opstrings function digests dr dobb s journal part i vol 30 no 7 cmp media llc pp 69 73 issn 1044 789x 374 archived from the original on 2020 03 02 retrieved 2020 03 02 schulman andrew 2005 08 01 finding binary clones with opstrings function digests dr dobb s journal part ii vol 30 no 8 cmp media llc pp 56 61 issn 1044 789x 375 archived from the original on 2020 03 02 retrieved 2016 05 28 schulman andrew 2005 09 01 finding binary clones with opstrings function digests cmp media llc part iii vol 30 no 9 united business media pp 64 70 issn 1044 789x 376 archived from the original on 2020 03 02 retrieved 2016 05 28 1 2 3 4 hennessy john l patterson david a asanović krste bakos jason d colwell robert p bhattacharjee abhishek conte thomas m duato josé franklin diana goldberg david jouppi norman p li sheng muralimanohar naveen peterson gregory d pinkston timothy m ranganathan parthasarathy wood david a young cliff zaky amr 2017 11 23 computer architecture a quantitative approach 6 ed cambridge massachusetts usa morgan kaufmann publishers isbn 978 0 12811905 1 oclc 983459758 mansfield richard 1983 introduction why machine language machine language for beginners compute books 1 ed greensboro north carolina usa compute publications inc american broadcasting companies inc small system services inc isbn 0 942386 11 6 archived from the original on 2008 02 13 retrieved 2016 05 28 tanenbaum andrew s austin todd 2013 structured computer organization sixth ed pearson education inc p 367 isbn 0 13 291652 5 bytecode definition pc magazine pc magazine encyclopedia archived from the original on 2012 10 06 retrieved 2015 10 10 v t e x86 assembly topics topics assembly language comparison of assemblers disassembler instruction set low level programming language machine code microassembler x86 assembly language assemblers a86 a386 flat assembler fasm gnu assembler gas high level assembly hla microsoft macro assembler masm netwide assembler nasm turbo assembler tasm open watcom assembler wasm programming issues call stack flags carry flag direction flag interrupt flag overflow flag zero flag memory address opcode program counter processor register calling conventions instruction listings registers retrieved from https en wikipedia org w index php title opcode oldid 1362920631 category machine code hidden categories articles with short description short description matches wikidata use dmy dates from march 2020 cs1 location test this page was last edited on 7 july 2026 at 00 29 utc page was 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