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Text of the page (random words):
ations resulting from decoding x86 instructions providing also the functionality of a micro operation cache having this the next time an instruction is needed it does not have to be decoded into micro ops again 42 63 68 write coalescing cache wcc edit write coalescing cache 43 is a special cache that is part of l2 cache in amd s bulldozer microarchitecture stores from both l1d caches in the module go through the wcc where they are buffered and coalesced the wcc s task is reducing number of writes to the l2 cache micro operation μop or uop cache edit a micro operation cache μop cache uop cache or uc 44 is a specialized cache that stores micro operations of decoded instructions as received directly from the instruction decoders or from the instruction cache when an instruction needs to be decoded the μop cache is checked for its decoded form which is re used if cached if it is not available the instruction is decoded and then cached one of the early works describing μop cache as an alternative frontend for the intel p6 processor family is the 2001 paper micro operation cache a power aware frontend for variable instruction length isa 45 later intel included μop caches in its sandy bridge processors and in successive microarchitectures like ivy bridge and haswell 42 121 123 46 amd implemented a μop cache in their zen microarchitecture 47 fetching complete pre decoded instructions eliminates the need to repeatedly decode variable length complex instructions into simpler fixed length micro operations and simplifies the process of predicting fetching rotating and aligning fetched instructions a μop cache effectively offloads the fetch and decode hardware thus decreasing power consumption and improving the frontend supply of decoded micro operations the μop cache also increases performance by more consistently delivering decoded micro operations to the backend and eliminating various bottlenecks in the cpu s fetch and decode logic 45 46 a μop cache has many similarities with a trace cache although a μop cache is much simpler thus providing better power efficiency this makes it better suited for implementations on battery powered devices the main disadvantage of the trace cache leading to its power inefficiency is the hardware complexity required for its heuristic deciding on caching and reusing dynamically created instruction traces 48 branch target instruction cache edit a branch target cache or branch target instruction cache the name used on arm microprocessors 49 is a specialized cache which holds the first few instructions at the destination of a taken branch this is used by low powered processors which do not need a normal instruction cache because the memory system is capable of delivering instructions fast enough to satisfy the cpu without one however this only applies to consecutive instructions in sequence it still takes several cycles of latency to restart instruction fetch at a new address causing a few cycles of pipeline bubble after a control transfer a branch target cache provides instructions for those few cycles avoiding a delay after most taken branches this allows full speed operation with a much smaller cache than a traditional full time instruction cache smart cache edit smart cache is a level 2 or level 3 caching method for multiple execution cores developed by intel smart cache shares the actual cache memory between the cores of a multi core processor in comparison to a dedicated per core cache the overall cache miss rate decreases when cores do not require equal parts of the cache space consequently a single core can use the full level 2 or level 3 cache while the other cores are inactive 50 furthermore the shared cache makes it faster to share memory among different execution cores 51 multi level caches edit see also cache hierarchy another issue is the fundamental tradeoff between cache latency and hit rate larger caches have better hit rates but longer latency to address this tradeoff many computers use multiple levels of cache with small fast caches backed up by larger slower caches multi level caches generally operate by checking the fastest but smallest cache level 1 l1 first if it hits the processor proceeds at high speed if that cache misses the slower but larger next level cache level 2 l2 is checked and so on before accessing external memory as the latency difference between main memory and the fastest cache has become larger some processors have begun to utilize as many as three levels of on chip cache price sensitive designs used this to pull the entire cache hierarchy on chip but by the 2010s some of the highest performance designs returned to having large off chip caches which is often implemented in edram and mounted on a multi chip module as a fourth cache level in rare cases such as in the mainframe cpu ibm z15 2019 all levels down to l1 are implemented by edram replacing sram entirely for cache registers are still typically implemented using sram based register files or flip flop based designs rather than edram 52 apple s arm based apple silicon series starting with the a14 and m1 have a 192 kib l1i cache for each of the high performance cores an unusually large amount however the high efficiency cores only have 128 kib since then other processors such as intel s lunar lake and qualcomm s oryon have also implemented similar l1i cache sizes the benefits of l3 and l4 caches depend on the application s access patterns examples of products incorporating l3 and l4 caches include the following alpha 21164 1995 had 1 to 64 mib off chip l3 cache amd k6 iii 1999 had motherboard based l3 cache ibm power4 2001 had off chip l3 caches of 32 mib per processor shared among several processors itanium 2 2003 had a 6 mib unified level 3 l3 cache on die the itanium 2 2003 mx 2 module incorporated two itanium 2 processors along with a shared 64 mib l4 cache on a multi chip module that was pin compatible with a madison processor intel s xeon mp product codenamed tulsa 2006 features 16 mib of on die l3 cache shared between two processor cores amd phenom 2007 with 2 mib of l3 cache amd phenom ii 2008 has up to 6 mib on die unified l3 cache intel core i7 2008 has an 8 mib on die unified l3 cache that is inclusive shared by all cores intel haswell cpus with integrated intel iris pro graphics have 128 mib of edram acting essentially as an l4 cache 53 finally at the other end of the memory hierarchy the cpu register file itself can be considered the smallest fastest cache in the system with the special characteristic that it is scheduled in software typically by a compiler as it allocates registers to hold values retrieved from main memory for as an example loop nest optimization however with register renaming most compiler register assignments are reallocated dynamically by hardware at runtime into a register bank allowing the cpu to break false data dependencies and thus easing pipeline hazards register files sometimes also have hierarchy the cray 1 circa 1976 had eight address a and eight scalar data s registers that were generally usable there was also a set of 64 address b and 64 scalar data t registers that took longer to access but were faster than main memory the b and t registers were provided because the cray 1 did not have a data cache the cray 1 did however have an instruction cache multi core chips edit when considering a chip with multiple cores there is a question of whether the caches should be shared or local to each core implementing shared cache inevitably introduces more wiring and complexity but then having one cache per chip rather than core greatly reduces the amount of space needed and thus one can include a larger cache typically sharing the l1 cache is undesirable because the resulting increase in latency would make each core run considerably slower than a single core chip however for the highest level cache usually l3 the last one called before accessing memory having a global cache is desirable for several reasons such as allowing a single core to use the whole cache reducing data redundancy by making it possible for different processes or threads to share cached data and reducing the complexity of utilized cache coherency protocols 54 for example an eight core chip with three levels may include an l1 cache for each core one intermediate l2 cache for each pair of cores and one l3 cache shared between all cores a shared highest level cache usually l3 called before accessing memory is usually referred to as a last level cache llc 55 additional techniques are used for increasing the level of parallelism when llc is shared between multiple cores including slicing it into multiple pieces which are addressing certain ranges of memory addresses and can be accessed independently 8 56 separate versus unified edit in a separate cache structure instructions and data are cached separately meaning that a cache line is used to cache either instructions or data but not both various benefits have been demonstrated with separate data and instruction translation lookaside buffers 57 in a unified structure this constraint is not present and cache lines can be used to cache both instructions and data exclusive versus inclusive edit multi level caches introduce new design decisions for instance in some processors all data in the l1 cache must also be somewhere in the l2 cache these caches are called strictly inclusive other processors like the amd athlon have exclusive caches data are guaranteed to be in at most one of the l1 and l2 caches never in both still other processors like the intel pentium ii iii and 4 do not require that data in the l1 cache also reside in the l2 cache although it may often do so there is no universally accepted name for this intermediate policy 58 59 two common names are non exclusive and partially inclusive the advantage of exclusive caches is that they store more data this advantage is larger when the exclusive l1 cache is comparable to the l2 cache and diminishes if the l2 cache is many times larger than the l1 cache when the l1 misses and the l2 hits on an access the hitting cache line in the l2 is exchanged with a line in the l1 this exchange is quite a bit more work than just copying a line from l2 to l1 which is what an inclusive cache does 59 one advantage of strictly inclusive caches is that when external devices or other processors in a multiprocessor system wish to remove a cache line from the processor they need only have the processor check the l2 cache in cache hierarchies which do not enforce inclusion the l1 cache must be checked as well as a drawback there is a correlation between the associativities of l1 and l2 caches if the l2 cache does not have at least as many ways as all l1 caches together the effective associativity of the l1 caches is restricted another disadvantage of inclusive cache is that whenever there is an eviction in l2 cache the possibly corresponding lines in l1 also have to get evicted in order to maintain inclusiveness this is quite a bit of work and would result in a higher l1 miss rate 59 another advantage of inclusive caches is that the larger cache can use larger cache lines which reduces the size of the secondary cache tags exclusive caches require both caches to have the same size cache lines so that cache lines can be swapped on a l1 miss l2 hit if the secondary cache is an order of magnitude larger than the primary and the cache data are an order of magnitude larger than the cache tags this tag area saved can be comparable to the incremental area needed to store the l1 cache data in the l2 60 scratchpad memory edit main article scratchpad memory scratchpad memory spm also known as scratchpad scratchpad ram or local store in computer terminology is a high speed internal memory used for temporary storage of calculations data and other work in progress example the k8 edit to illustrate both specialization and multi level caching here is the cache hierarchy of the k8 core in the amd athlon 64 cpu 61 cache hierarchy of the k8 core in the amd athlon 64 cpu the k8 has four specialized caches an instruction cache an instruction tlb a data tlb and a data cache each of these caches is specialized the instruction cache keeps copies of 64 byte lines of memory and fetches 16 bytes each cycle each byte in this cache is stored in ten bits rather than eight with the extra bits marking the boundaries of instructions this is an example of predecoding the cache has only parity protection rather than ecc because parity is smaller and any damaged data can be replaced by fresh data fetched from memory which always has an up to date copy of instructions the instruction tlb keeps copies of page table entries ptes each cycle s instruction fetch has its virtual address translated through this tlb into a physical address each entry is either four or eight bytes in memory because the k8 has a variable page size each of the tlbs is split into two sections one to keep ptes that map 4 kib pages and one to keep ptes that map 4 mib or 2 mib pages the split allows the fully associative match circuitry in each section to be simpler the operating system maps different sections of the virtual address space with different size ptes the data tlb has two copies which keep identical entries the two copies allow two data accesses per cycle to translate virtual addresses to physical addresses like the instruction tlb this tlb is split into two kinds of entries the data cache keeps copies of 64 byte lines of memory it is split into 8 banks each storing 8 kib of data and can fetch two 8 byte data each cycle so long as those data are in different banks there are two copies of the tags because each 64 byte line is spread among all eight banks each tag copy handles one of the two accesses per cycle the k8 also has multiple level caches there are second level instruction and data tlbs which store only ptes mapping 4 kib both instruction and data caches and the various tlbs can fill from the large unified l2 cache this cache is exclusive to both the l1 instruction and data caches which means that any 8 byte line can only be in one of the l1 instruction cache the l1 data cache or the l2 cache it is however possible for a line in the data cache to have a pte which is also in one of the tlbs the operating system is responsible for keeping the tlbs coherent by flushing portions of them when the page tables in memory are updated the k8 also caches information that is never stored in memory prediction information these caches are not shown in the above diagram as is usual for this class of cpu the k8 has fairly complex branch prediction with tables that help predict whether branches are taken and other tables which predict the targets of branches and jumps some of this information is associated with instructions in both the level 1 instruction cache and the unified secondary cache the k8 uses an interesting trick to store prediction information with instructions in the secondary ...
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