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Text of the page (random words):
ore power and chip area and potentially more time on the other hand caches with more associativity suffer fewer misses see conflict misses so that the cpu wastes less time reading from the slow main memory the general guideline is that doubling the associativity from direct mapped to two way or from two way to four way has about the same effect on raising the hit rate as doubling the cache size however increasing associativity more than four does not improve hit rate as much 13 and are generally done for other reasons see virtual aliasing some cpus can dynamically reduce the associativity of their caches in low power states which acts as a power saving measure 14 in order of worse but simple to better but complex direct mapped cache good best case time but unpredictable in the worst case two way set associative cache two way skewed associative cache 15 four way set associative cache eight way set associative cache a common choice for later implementations 12 way set associative cache similar to eight way fully associative cache the best miss rates but practical only for a small number of entries direct mapped cache edit in this cache organization each location in the main memory can go in only one entry in the cache therefore a direct mapped cache can also be called a one way set associative cache it does not have a placement policy as such since there is no choice of which cache entry s contents to evict this means that if two locations map to the same entry they may continually knock each other out although simpler a direct mapped cache needs to be much larger than an associative one to give comparable performance and it is more unpredictable let x be block number in cache y be block number of memory and n be number of blocks in cache then mapping is done with the help of the equation x y mod n two way set associative cache edit if each location in the main memory can be cached in either of two locations in the cache one logical question is which one of the two the simplest and most commonly used scheme shown in the right hand diagram above is to use the least significant bits of the memory location s index as the index for the cache memory and to have two entries for each index one benefit of this scheme is that the tags stored in the cache do not have to include that part of the main memory address which is implied by the cache memory s index since the cache tags have fewer bits they require fewer transistors take less space on the processor circuit board or on the microprocessor chip and can be read and compared faster also lru algorithm is especially simple since only one bit needs to be stored for each pair speculative execution edit one of the advantages of a direct mapped cache is that it allows simple and fast speculation once the address has been computed the one cache index which might have a copy of that location in memory is known that cache entry can be read and the processor can continue to work with that data before it finishes checking that the tag actually matches the requested address the idea of having the processor use the cached data before the tag match completes can be applied to associative caches as well a subset of the tag called a hint can be used to pick just one of the possible cache entries mapping to the requested address the entry selected by the hint can then be used in parallel with checking the full tag the hint technique works best when used in the context of address translation as explained below two way skewed associative cache edit other schemes have been suggested such as the skewed cache 15 where the index for way 0 is direct as above but the index for way 1 is formed with a hash function a good hash function has the property that addresses which conflict with the direct mapping tend not to conflict when mapped with the hash function and so it is less likely that a program will suffer from an unexpectedly large number of conflict misses due to a pathological access pattern the downside is extra latency from computing the hash function 16 additionally when it comes time to load a new line and evict an old line it may be difficult to determine which existing line was least recently used because the new line conflicts with data at different indexes in each way lru tracking for non skewed caches is usually done on a per set basis nevertheless skewed associative caches have major advantages over conventional set associative ones 17 pseudo associative cache edit a true set associative cache tests all the possible ways simultaneously using something like a content addressable memory a pseudo associative cache tests each possible way one at a time a hash rehash cache and a column associative cache are examples of a pseudo associative cache in the common case of finding a hit in the first way tested a pseudo associative cache is as fast as a direct mapped cache but it has a much lower conflict miss rate than a direct mapped cache closer to the miss rate of a fully associative cache 16 multicolumn cache edit comparing with a direct mapped cache a set associative cache has a reduced number of bits for its cache set index that maps to a cache set where multiple ways or blocks stays such as 2 blocks for a 2 way set associative cache and 4 blocks for a 4 way set associative cache comparing with a direct mapped cache the unused cache index bits become a part of the tag bits for example a 2 way set associative cache contributes 1 bit to the tag and a 4 way set associative cache contributes 2 bits to the tag the basic idea of the multicolumn cache 18 is to use the set index to map to a cache set as a conventional set associative cache does and to use the added tag bits to index a way in the set for example in a 4 way set associative cache the two bits are used to index way 00 way 01 way 10 and way 11 respectively this double cache indexing is called a major location mapping and its latency is equivalent to a direct mapped access extensive experiments in multicolumn cache design 18 shows that the hit ratio to major locations is as high as 90 if cache mapping conflicts with a cache block in the major location the existing cache block will be moved to another cache way in the same set which is called selected location because the newly indexed cache block is a most recently used mru block it is placed in the major location in multicolumn cache with a consideration of temporal locality since multicolumn cache is designed for a cache with a high associativity the number of ways in each set is high thus it is easy find a selected location in the set a selected location index by an additional hardware is maintained for the major location in a cache block citation needed multicolumn cache remains a high hit ratio due to its high associativity and has a comparable low latency to a direct mapped cache due to its high percentage of hits in major locations the concepts of major locations and selected locations in multicolumn cache have been used in several cache designs in arm cortex r chip 19 intel s way predicting cache memory 20 ibm s reconfigurable multi way associative cache memory 21 and oracle s dynamic cache replacement way selection based on address tab bits 22 cache entry structure edit cache row entries usually have the following structure tag data block flag bits the data block cache line contains the actual data fetched from the main memory the tag contains part of the address of the actual data fetched from the main memory the flag bits are discussed below the size of the cache is the amount of main memory data it can hold this size can be calculated as the number of bytes stored in each data block times the number of blocks stored in the cache the tag flag and error correction code bits are not included in the size 23 although they do affect the physical area of a cache an effective memory address which goes along with the cache line memory block is split msb to lsb into the tag the index and the block offset 8 24 tag index block offset the index describes which cache set that the data has been put in the index length is log 2 s displaystyle lceil log _ 2 s rceil bits for s cache sets the block offset specifies the desired data within the stored data block within the cache row typically the effective address is in bytes so the block offset length is log 2 b displaystyle lceil log _ 2 b rceil bits where b is the number of bytes per data block the tag contains the most significant bits of the address which are checked against all rows in the current set the set has been retrieved by index to see if this set contains the requested address if it does a cache hit occurs the tag length in bits is as follows tag_length address_length index_length block_offset_length some authors refer to the block offset as simply the offset 25 or the displacement 26 27 example edit the original pentium 4 processor had a four way set associative l1 data cache of 8 kib in size with 64 byte cache blocks hence there are 8 kib 64 128 cache blocks the number of sets is equal to the number of cache blocks divided by the number of ways of associativity what leads to 128 4 32 sets and hence 2 5 32 different indices there are 2 6 64 possible offsets since the cpu address is 32 bits wide this implies 32 5 6 21 bits for the tag field the original pentium 4 processor also had an eight way set associative l2 integrated cache 256 kib in size with 128 byte cache blocks this implies 32 8 7 17 bits for the tag field 25 flag bits edit an instruction cache requires only one flag bit per cache row entry a valid bit the valid bit indicates whether or not a cache block has been loaded with valid data on power up the hardware sets all the valid bits in all the caches to invalid some systems also set a valid bit to invalid at other times such as when multi master bus snooping hardware in the cache of one processor hears an address broadcast from some other processor and realizes that certain data blocks in the local cache are now stale and should be marked invalid a data cache typically requires two flag bits per cache line a valid bit and a dirty bit having a dirty bit set indicates that the associated cache line has been changed since it was read from main memory dirty meaning that the processor has written data to that line and the new value has not propagated all the way to main memory cache miss edit a cache miss is a failed attempt to read or write a piece of data in the cache which results in a main memory access with much longer latency there are three kinds of cache misses instruction read miss data read miss and data write miss cache read misses from an instruction cache generally cause the largest delay because the processor or at least the thread of execution has to wait stall until the instruction is fetched from main memory cache read misses from a data cache usually cause a smaller delay because instructions not dependent on the cache read can be issued and continue execution until the data are returned from main memory and the dependent instructions can resume execution cache write misses to a data cache generally cause the shortest delay because the write can be queued and there are few limitations on the execution of subsequent instructions the processor can continue until the queue is full for a detailed introduction to the types of misses see cache performance measurement and metric address translation edit most general purpose cpus implement some form of virtual memory to summarize either each program running on the machine sees its own simplified address space which contains code and data for that program only or all programs run in a common virtual address space a program executes by calculating comparing reading and writing to addresses of its virtual address space rather than addresses of physical address space making programs simpler and thus easier to write virtual memory requires the processor to translate virtual addresses generated by the program into physical addresses in main memory the portion of the processor that does this translation is known as the memory management unit mmu the fast path through the mmu can perform those translations stored in the translation lookaside buffer tlb which is a cache of mappings from the operating system s page table segment table or both for the purposes of the present discussion there are three important features of address translation latency the physical address is available from the mmu some time perhaps a few cycles after the virtual address is available from the address generator aliasing multiple virtual addresses can map to a single physical address most processors guarantee that all updates to that single physical address will happen in program order to deliver on that guarantee the processor must ensure that only one copy of a physical address resides in the cache at any given time granularity the virtual address space is broken up into pages for instance a 4 gib virtual address space might be cut up into 1 048 576 pages of 4 kib size each of which can be independently mapped there may be multiple page sizes supported see virtual memory for elaboration one early virtual memory system the ibm m44 44x required an access to a mapping table held in core memory before every programmed access to main memory 28 nb 1 with no caches and with the mapping table memory running at the same speed as main memory this effectively cut the speed of memory access in half two early machines that used a page table in main memory for mapping the ibm system 360 model 67 and the ge 645 both had a small associative memory as a cache for accesses to the in memory page table both machines predated the first machine with a cache for main memory the ibm system 360 model 85 so the first hardware cache used in a computer system was not a data or instruction cache but rather a tlb caches can be divided into four types based on whether the index or tag correspond to physical or virtual addresses physically indexed physically tagged pipt caches use the physical address for both the index and the tag while this is simple and avoids problems with aliasing it is also slow as the physical address must be looked up which could involve a tlb miss and access to main memory before that address can be looked up in the cache virtually indexed virtually tagged vivt caches use the virtual address for both the index and the tag this caching scheme can result in much faster lookups since the mmu does not need to be consulted first to determine the physical address for a given virtual address however vivt suffers from aliasing problems where several different virtual addresses may refer to the same physical address the result is that such addresses would be cached separately despite referring to the same memory causing coherency problems although solutions to this problem exist 31 they do not work for standard coherence protocols another problem is homonyms where the same virtual address maps to seve...
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