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Text of the page (random words):
happened much later for l1 caches as their size is generally still a small number of kib the ibm zec12 from 2012 is an exception however to gain unusually large 96 kib l1 data cache for its time and e g the ibm z13 having a 96 kib l1 instruction cache and 128 kib l1 data cache 9 and intel ice lake based processors from 2018 having 48 kib l1 data cache and 48 kib l1 instruction cache in 2020 some intel atom cpus with up to 24 cores have multiple of 4 5 mib and 15 mib cache sizes 10 11 operation edit cache entries edit data is transferred between memory and cache in blocks of fixed size called cache lines or cache blocks when a cache line is copied from memory into the cache a cache entry is created the cache entry will include the copied data as well as the requested memory location called a tag when the processor needs to read or write a location in memory it first checks for a corresponding entry in the cache the cache checks for the contents of the requested memory location in any cache lines that might contain that address if the processor finds that the memory location is in the cache a cache hit has occurred however if the processor does not find the memory location in the cache a cache miss has occurred in the case of a cache hit the processor immediately reads or writes the data in the cache line for a cache miss the cache allocates a new entry and copies data from main memory then the request is fulfilled from the contents of the cache policies edit replacement policies edit main article cache replacement policies to make room for the new entry on a cache miss the cache may have to evict one of the existing entries the heuristic it uses to choose the entry to evict is called the replacement policy the fundamental problem with any replacement policy is that it must predict which existing cache entry is least likely to be used in the future predicting the future is generally difficult so there is no perfect method to choose among the variety of replacement policies available one popular replacement policy least recently used lru replaces the least recently accessed entry marking some memory ranges as non cacheable can improve performance by avoiding caching of memory regions that are rarely re accessed this avoids the overhead of loading something into the cache without having any reuse cache entries may also be disabled or locked depending on the context write policies edit main article cache computing writing policies if data are written to the cache at some point they must also be written to main memory the timing of this write is known as the write policy in a write through cache every write to the cache causes a write to main memory alternatively in a write back or copy back cache writes are not immediately mirrored to the main memory with locations been written over being marked as dirty being written back to the main memory only when they are evicted from the cache for this reason a read miss in a write back cache may sometimes require two memory accesses to service one to first write the dirty location to main memory and then another to read the new location from memory also a write to a main memory location that is not yet mapped in a write back cache may evict an already dirty location thereby freeing that cache space for the new memory location there are intermediate policies as well the cache may be write through but the writes may be held in a store data queue temporarily usually so multiple stores can be processed together which can reduce bus turnarounds and improve bus utilization cached data from the main memory may be changed by other entities e g peripherals using direct memory access dma or another core in a multi core processor in which case the copy in the cache may become out of date or stale alternatively when a cpu in a multiprocessor system updates data in the cache copies of data in caches associated with other cpus become stale communication protocols between the cache managers that keep the data consistent are known as cache coherence protocols cache performance edit cache performance measurement has become important in recent times where the speed gap between the memory performance and the processor performance is increasing exponentially the cache was introduced to reduce this speed gap thus knowing how well the cache is able to bridge the gap in the speed of processor and memory becomes important especially in high performance systems the cache hit rate and the cache miss rate play an important role in determining this performance to improve the cache performance reducing the miss rate becomes one of the necessary steps among other steps decreasing the access time to the cache also gives a boost to its performance and helps with optimization cpu stalls edit the time taken to fetch one cache line from memory read latency due to a cache miss matters because the cpu will run out of work while waiting for the cache line when a cpu reaches this state it is called a stall as cpus become faster compared to main memory stalls due to cache misses displace more potential computation modern cpus can execute hundreds of instructions in the time taken to fetch a single cache line from main memory various techniques have been employed to keep the cpu busy during this time including out of order execution in which the cpu attempts to execute independent instructions after the instruction that is waiting for the cache miss data another technology used by many processors is simultaneous multithreading smt which allows an alternate thread to use the cpu core while the first thread waits for required cpu resources to become available associativity edit main article cache placement policies an illustration of different ways in which memory locations can be cached by particular cache locations the placement policy decides where in the cache a copy of a particular entry of main memory will go if the placement policy is free to choose any entry in the cache to hold the copy the cache is called fully associative at the other extreme if each entry in the main memory can go in just one place in the cache the cache is direct mapped many caches implement a compromise in which each entry in the main memory can go to any one of n places in the cache and are described as n way set associative 12 for example the level 1 data cache in an amd athlon is two way set associative which means that any particular location in main memory can be cached in either of two locations in the level 1 data cache choosing the right value of associativity involves a trade off if there are ten places to which the placement policy could have mapped a memory location then to check if that location is in the cache ten cache entries must be searched checking more places takes more power and chip area and potentially more time on the other hand caches with more associativity suffer fewer misses see conflict misses so that the cpu wastes less time reading from the slow main memory the general guideline is that doubling the associativity from direct mapped to two way or from two way to four way has about the same effect on raising the hit rate as doubling the cache size however increasing associativity more than four does not improve hit rate as much 13 and are generally done for other reasons see virtual aliasing some cpus can dynamically reduce the associativity of their caches in low power states which acts as a power saving measure 14 in order of worse but simple to better but complex direct mapped cache good best case time but unpredictable in the worst case two way set associative cache two way skewed associative cache 15 four way set associative cache eight way set associative cache a common choice for later implementations 12 way set associative cache similar to eight way fully associative cache the best miss rates but practical only for a small number of entries direct mapped cache edit in this cache organization each location in the main memory can go in only one entry in the cache therefore a direct mapped cache can also be called a one way set associative cache it does not have a placement policy as such since there is no choice of which cache entry s contents to evict this means that if two locations map to the same entry they may continually knock each other out although simpler a direct mapped cache needs to be much larger than an associative one to give comparable performance and it is more unpredictable let x be block number in cache y be block number of memory and n be number of blocks in cache then mapping is done with the help of the equation x y mod n two way set associative cache edit if each location in the main memory can be cached in either of two locations in the cache one logical question is which one of the two the simplest and most commonly used scheme shown in the right hand diagram above is to use the least significant bits of the memory location s index as the index for the cache memory and to have two entries for each index one benefit of this scheme is that the tags stored in the cache do not have to include that part of the main memory address which is implied by the cache memory s index since the cache tags have fewer bits they require fewer transistors take less space on the processor circuit board or on the microprocessor chip and can be read and compared faster also lru algorithm is especially simple since only one bit needs to be stored for each pair speculative execution edit one of the advantages of a direct mapped cache is that it allows simple and fast speculation once the address has been computed the one cache index which might have a copy of that location in memory is known that cache entry can be read and the processor can continue to work with that data before it finishes checking that the tag actually matches the requested address the idea of having the processor use the cached data before the tag match completes can be applied to associative caches as well a subset of the tag called a hint can be used to pick just one of the possible cache entries mapping to the requested address the entry selected by the hint can then be used in parallel with checking the full tag the hint technique works best when used in the context of address translation as explained below two way skewed associative cache edit other schemes have been suggested such as the skewed cache 15 where the index for way 0 is direct as above but the index for way 1 is formed with a hash function a good hash function has the property that addresses which conflict with the direct mapping tend not to conflict when mapped with the hash function and so it is less likely that a program will suffer from an unexpectedly large number of conflict misses due to a pathological access pattern the downside is extra latency from computing the hash function 16 additionally when it comes time to load a new line and evict an old line it may be difficult to determine which existing line was least recently used because the new line conflicts with data at different indexes in each way lru tracking for non skewed caches is usually done on a per set basis nevertheless skewed associative caches have major advantages over conventional set associative ones 17 pseudo associative cache edit a true set associative cache tests all the possible ways simultaneously using something like a content addressable memory a pseudo associative cache tests each possible way one at a time a hash rehash cache and a column associative cache are examples of a pseudo associative cache in the common case of finding a hit in the first way tested a pseudo associative cache is as fast as a direct mapped cache but it has a much lower conflict miss rate than a direct mapped cache closer to the miss rate of a fully associative cache 16 multicolumn cache edit comparing with a direct mapped cache a set associative cache has a reduced number of bits for its cache set index that maps to a cache set where multiple ways or blocks stays such as 2 blocks for a 2 way set associative cache and 4 blocks for a 4 way set associative cache comparing with a direct mapped cache the unused cache index bits become a part of the tag bits for example a 2 way set associative cache contributes 1 bit to the tag and a 4 way set associative cache contributes 2 bits to the tag the basic idea of the multicolumn cache 18 is to use the set index to map to a cache set as a conventional set associative cache does and to use the added tag bits to index a way in the set for example in a 4 way set associative cache the two bits are used to index way 00 way 01 way 10 and way 11 respectively this double cache indexing is called a major location mapping and its latency is equivalent to a direct mapped access extensive experiments in multicolumn cache design 18 shows that the hit ratio to major locations is as high as 90 if cache mapping conflicts with a cache block in the major location the existing cache block will be moved to another cache way in the same set which is called selected location because the newly indexed cache block is a most recently used mru block it is placed in the major location in multicolumn cache with a consideration of temporal locality since multicolumn cache is designed for a cache with a high associativity the number of ways in each set is high thus it is easy find a selected location in the set a selected location index by an additional hardware is maintained for the major location in a cache block citation needed multicolumn cache remains a high hit ratio due to its high associativity and has a comparable low latency to a direct mapped cache due to its high percentage of hits in major locations the concepts of major locations and selected locations in multicolumn cache have been used in several cache designs in arm cortex r chip 19 intel s way predicting cache memory 20 ibm s reconfigurable multi way associative cache memory 21 and oracle s dynamic cache replacement way selection based on address tab bits 22 cache entry structure edit cache row entries usually have the following structure tag data block flag bits the data block cache line contains the actual data fetched from the main memory the tag contains part of the address of the actual data fetched from the main memory the flag bits are discussed below the size of the cache is the amount of main memory data it can hold this size can be calculated as the number of bytes stored in each data block times the number of blocks stored in the cache the tag flag and error correction code bits are not included in the size 23 although they do affect the physical area of a cache an effective memory address which goes along with the cache line memory block is split msb to lsb into the tag the index and the block offset 8 24 tag index block offset the index describes which cache set that the data has been put in the index length is log 2 s displaystyle lceil log _ 2 s rceil bits for s cache sets the block offset specifies the desired data...
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