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in automotive electronics 29 30 27 rf dmos also known as rf power mosfet is a type of dmos power transistor designed for radio frequency rf applications it is used in various radio and rf applications 31 32 power mosfets including dmos ldmos and vmos are commonly used for a wide range of other applications 33 34 35 basic structure edit fig 1 cross section of a vdmos showing an elementary cell note that a cell is very small some micrometres to some tens of micrometres wide and that a power mosfet is composed of several thousand of them several structures had been explored in the 1970s when the first commercial power mosfets were introduced however most of them have been abandoned at least until recently in favour of the vertical diffused mos vdmos structure also called double diffused mos or simply dmos and the ldmos laterally diffused mos structure the cross section of a vdmos see figure 1 shows the verticality of the device it can be seen that the source electrode is placed over the drain resulting in a current mainly vertical when the transistor is in the on state the diffusion in vdmos refers to the manufacturing process the p wells see figure 1 are obtained by a diffusion process actually a double diffusion process to get the p and n regions hence the name double diffused power mosfets have a different structure from the lateral mosfet as with most power devices their structure is vertical and not planar in a planar structure the current and breakdown voltage ratings are both functions of the channel dimensions respectively width and length of the channel resulting in inefficient use of the silicon real estate with a vertical structure the voltage rating of the transistor is a function of the doping and thickness of the n epitaxial layer see cross section while the current rating is a function of the channel width this makes it possible for the transistor to sustain both high blocking voltage and high current within a compact piece of silicon ldmos are power mosfets with a lateral structure they are mainly used in high end audio power amplifiers 16 and rf power amplifiers in wireless cellular networks such as 2g 3g 17 and 4g 18 their advantage is a better behaviour in the saturated region corresponding to the linear region of a bipolar junction transistor than the vertical mosfets vertical mosfets are designed for switching applications so they are only used in on or off states on state resistance edit fig 2 contribution of the different parts of the mosfet to the on state resistance when the power mosfet is in the on state see mosfet for a discussion on operation modes it exhibits a resistive behaviour between the drain and source terminals it can be seen in figure 2 that this resistance called r dson for drain to source resistance in on state is the sum of many elementary contributions r s is the source resistance it represents all resistances between the source terminal of the package to the channel of the mosfet resistance of the bond wires of the source metallisation and of the n wells r ch this is the channel resistance it is inversely proportional to the channel width and for a given die size to the channel density the channel resistance is one of the main contributors to the r dson of low voltage mosfets and intensive work has been carried out to reduce their cell size in order to increase the channel density r a is the access resistance it represents the resistance of the epitaxial zone directly under the gate electrode where the direction of the current changes from horizontal in the channel to vertical to the drain contact r jfet is the detrimental effect of the cell size reduction mentioned above the p implantations see figure 1 form the gates of a parasitic jfet transistor that tend to reduce the width of the current flow r n is the resistance of the epitaxial layer as the role of this layer is to sustain the blocking voltage r n is directly related to the voltage rating of the device a high voltage mosfet requires a thick low doped layer i e highly resistive whereas a low voltage transistor only requires a thin layer with a higher doping level i e less resistive as a result r n is the main factor responsible for the resistance of high voltage mosfets r d is the equivalent of r s for the drain it represents the resistance of the transistor substrate the cross section in figure 1 is not at scale the bottom n layer is actually the thickest and of the package connections breakdown voltage on state resistance trade off edit fig 3 the r dson of mosfets increases with their voltage rating when in the off state the power mosfet is equivalent to a pin diode constituted by the p diffusion the n epitaxial layer and the n substrate when this highly non symmetrical structure is reverse biased the space charge region extends principally on the lightly doped side i e over the n layer this means that this layer has to withstand most of the mosfet s off state drain to source voltage however when the mosfet is in the on state this n layer has no function furthermore as it is a lightly doped region its intrinsic resistivity is non negligible and adds to the mosfet s on state drain to source resistance r dson this is the r n resistance in figure 2 two main parameters govern both the breakdown voltage and the r dson of the transistor the doping level and the thickness of the n epitaxial layer the thicker the layer and the lower its doping level the higher the breakdown voltage on the contrary the thinner the layer and the higher the doping level the lower the r dson and therefore the lower the conduction losses of the mosfet therefore it can be seen that there is a trade off in the design of a mosfet between its voltage rating and its on state resistance citation needed this is demonstrated by the plot in figure 3 body diode edit it can be seen in figure 1 that the source metallization connects both the n and p implantations although the operating principle of the mosfet only requires the source to be connected to the n zone however if it were this would result in a floating p zone between the n doped source and drain which is equivalent to a npn transistor with a non connected base under certain conditions under high drain current when the on state drain to source voltage is in the order of some volts this parasitic npn transistor would be triggered making the mosfet uncontrollable the connection of the p implantation to the source metallization shorts the base of the parasitic transistor to its emitter the source of the mosfet and thus prevents spurious latching this solution however creates a diode between the drain cathode and the source anode of the mosfet making it able to block current in only one direction body diodes may be utilized as freewheeling diodes for inductive loads in configurations such as h bridge or half bridge while these diodes usually have rather high forward voltage drop they can handle large currents and are sufficient in many applications reducing part count and thus device cost and board space to increase efficiency synchronous rectification is often used to minimize the amount of time that the body diode conducts current switching operation edit fig 4 location of the intrinsic capacitances of a power mosfet because of its unipolar nature the power mosfet can switch at very high speed indeed there is no need to remove minority carriers as with bipolar devices the only intrinsic limitation in commutation speed is due to the internal capacitances of the mosfet see figure 4 these capacitances must be charged or discharged when the transistor switches this can be a relatively slow process because the current that flows through the gate capacitances is limited by the external driver circuit this circuit will actually dictate the commutation speed of the transistor assuming the power circuit has sufficiently low inductance further information mosfet gate driver capacitances edit in the mosfet datasheets the capacitances are often named c iss input capacitance drain and source terminal shorted c oss output capacitance gate and source shorted and c rss reverse transfer capacitance source connected to ground the relationship between these capacitances and those described below is c i s s c g s c g d c o s s c g d c d s c r s s c g d displaystyle begin matrix c_ iss c_ gs c_ gd c_ oss c_ gd c_ ds c_ rss c_ gd end matrix where c gs c gd and c ds are respectively the gate to source gate to drain and drain to source capacitances see below manufacturers prefer to quote c iss c oss and c rss because they can be directly measured on the transistor however as c gs c gd and c ds are closer to the physical meaning they will be used in the remaining of this article gate to source capacitance edit the c gs capacitance is constituted by the parallel connection of c oxn c oxp and c oxm see figure 4 as the n and p regions are highly doped the two former capacitances can be considered as constant c oxm is the capacitance between the polysilicon gate and the metal source electrode so it is also constant therefore it is common practice to consider c gs as a constant capacitance i e its value does not depend on the transistor state gate to drain capacitance edit the c gd capacitance can be seen as the connection in series of two elementary capacitances the first one is the oxide capacitance c oxd constituted by the gate electrode the silicon dioxide and the top of the n epitaxial layer it has a constant value the second capacitance c gdj is caused by the extension of the space charge zone when the mosfet is in off state therefore it is dependent upon the drain to gate voltage from this the value of c gd is c g d c o x d c g d j v g d c o x d c g d j v g d displaystyle c_ gd frac c_ oxd times c_ gdj left v_ gd right c_ oxd c_ gdj left v_ gd right the width of the space charge region is given by 36 w g d j 2 ϵ s i v g d q n displaystyle w_ gdj sqrt frac 2 epsilon _ si v_ gd qn where ϵ s i displaystyle epsilon _ si is the permittivity of the silicon q is the electron charge and n is the doping level the value of c gdj can be approximated using the expression of the plane capacitor c g d j a g d ϵ s i w g d j displaystyle c_ gdj a_ gd frac epsilon _ si w_ gdj where a gd is the surface area of the gate drain overlap therefore it comes c g d j v g d a g d q ϵ s i n 2 v g d displaystyle c_ gdj left v_ gd right a_ gd sqrt frac q epsilon _ si n 2v_ gd it can be seen that c gdj and thus c gd is a capacitance whose value is dependent upon the gate to drain voltage as this voltage increases the capacitance decreases when the mosfet is in on state c gdj is shunted so the gate to drain capacitance remains equal to c oxd a constant value drain to source capacitance edit as the source metallization overlaps the p wells see figure 1 the drain and source terminals are separated by a p n junction therefore c ds is the junction capacitance this is a non linear capacitance and its value can be calculated using the same equation as for c gdj other dynamic elements edit equivalent circuit of a power mosfet including the dynamic elements capacitors inductors the parasitic resistors the body diode packaging inductances edit to operate the mosfet must be connected to the external circuit most of the time using wire bonding although alternative techniques are investigated these connections exhibit a parasitic inductance which is in no way specific to the mosfet technology but has important effects because of the high commutation speeds parasitic inductances tend to maintain their current constant and generate overvoltage during the transistor turn off resulting in increasing commutation losses a parasitic inductance can be associated with each terminal of the mosfet they have different effects the gate inductance has little influence assuming it is lower than some hundreds of nanohenries because the current gradients on the gate are relatively slow in some cases however the gate inductance and the input capacitance of the transistor can constitute an oscillator this must be avoided as it results in very high commutation losses up to the destruction of the device on a typical design parasitic inductances are kept low enough to prevent this phenomenon the drain inductance tends to reduce the drain voltage when the mosfet turns on so it reduces turn on losses however as it creates an overvoltage during turn off it increases turn off losses the source parasitic inductance has the same behaviour as the drain inductance plus a feedback effect that makes commutation last longer thus increasing commutation losses at the beginning of a fast turn on due to the source inductance the voltage at the source on the die will be able to jump up as well as the gate voltage the internal v gs voltage will remain low for a longer time therefore delaying turn on at the beginning of a fast turn off as current through the source inductance decreases sharply the resulting voltage across it goes negative with respect to the lead outside the package raising the internal v gs voltage keeping the mosfet on and therefore delaying turn off limits of operation edit gate oxide breakdown edit the gate oxide is very thin 100 nm or less so it can only sustain a limited voltage in the datasheets manufacturers often state a maximum gate to source voltage around 20 v and exceeding this limit can result in destruction of the component furthermore a high gate to source voltage reduces significantly the lifetime of the mosfet with little to no advantage on r dson reduction to deal with this issue a gate driver circuit is often used maximum drain to source voltage edit power mosfets have a maximum specified drain to source voltage in the off state beyond which breakdown may occur exceeding the breakdown voltage causes the device to conduct potentially damaging it and other circuit elements due to excessive power dissipation maximum drain current edit the drain current must generally stay below a certain specified value maximum continuous drain current it can reach higher values for very short durations of time maximum pulsed drain current sometimes specified for various pulse durations the drain current is limited by heating due to resistive losses in internal components such as bond wires and other phenomena such as electromigration in the metal layer maximum temperature edit the junction temperature t j of the mosfet must stay under a specified maximum value for the device to function reliably determined by mosfet die layout and packaging materials the packaging often limits the maximum junction temperature due to the molding compound and where used epoxy characteristics the maximum operating ambient temperature is determined by the power dissipation and thermal resistance the junction to case thermal resistance is intrinsic to the device and package the case to ambient thermal resistance is largely dependent on the board mounting layout heatsinking area and air fluid flow the t...
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