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hazard computer architecture wikipedia jump to content main menu main menu move to sidebar hide navigation main page contents current events random article about wikipedia contact us contribute help learn to edit community portal recent changes upload file special pages search search appearance donate create account log in personal tools donate create account log in contents move to sidebar hide top 1 background 2 types toggle types subsection 2 1 structural hazards 2 2 control hazards branch hazards or instruction hazards 3 pipeline bubbling toggle pipeline bubbling subsection 3 1 data hazards 3 1 1 operand forwarding 3 1 2 examples 3 2 control hazards branch hazards 3 3 other techniques 4 see also 5 references toggle references subsection 5 1 general 6 external links toggle the table of contents hazard computer architecture 7 languages deutsch español فارسی српски srpski türkçe українська 中文 edit links article talk english read edit view history tools tools move to sidebar hide actions read edit view history general what links here related changes upload file permanent link page information cite this page get shortened url switch to legacy parser print export download as pdf printable version in other projects wikidata item appearance move to sidebar hide from wikipedia the free encyclopedia redirected from control hazard problems with central processing unit design this article needs more citations please help improve this article by adding citations to reliable sources unsourced material may be challenged and removed find sources hazard computer architecture news newspapers books scholar jstor january 2014 learn how and when to remove this message in the domain of central processing unit cpu design hazards are problems with the instruction pipeline in cpu microarchitectures when the next instruction cannot execute in the following clock cycle 1 and can potentially lead to incorrect computation results three common types of hazards are data hazards structural hazards and control hazards branching hazards 2 there are several methods used to deal with hazards including pipeline stalls pipeline bubbling operand forwarding and in the case of out of order execution the scoreboarding method and the tomasulo algorithm background edit further information instruction pipelining instructions in a pipelined processor are performed in several stages so that at any given time several instructions are being processed in the various stages of the pipeline such as fetch and execute there are many different instruction pipeline microarchitectures and instructions may be executed out of order a hazard occurs when two or more of these simultaneous possibly out of order instructions conflict types edit structural hazards edit a structural hazard occurs when two or more instructions which are already in a pipeline need the same resource the result is that instructions must be executed in series rather than in parallel for a portion of the pipeline structural hazards are sometimes referred to as resource hazards example a situation in which multiple instructions are ready to enter the execution phase but there is a single alu arithmetic logic unit one solution to this resource hazard is to increase available resources by having multiple ports into main memory and multiple alus control hazards branch hazards or instruction hazards edit control hazard occurs when the control logic incorrectly predicts which program branch will be taken and therefore brings a sequence of instructions into the pipeline that are subsequently discarded the term branch hazard also refers to a control hazard pipeline bubbling edit main article bubble computing bubbling the pipeline also termed a pipeline break or pipeline stall is a method to preclude data structural and branch hazards as instructions are fetched control logic determines whether a hazard could will occur if this is true then the control logic inserts no operation s nop s into the pipeline thus before the next instruction which would cause the hazard executes the prior one will have had sufficient time to finish and prevent the hazard if the number of nop s equals the number of stages in the pipeline the processor has been cleared of all instructions and can proceed free from hazards all forms of stalling introduce a delay before the processor can resume execution flushing the pipeline occurs when a branch instruction jumps to a new memory location invalidating all prior stages in the pipeline these prior stages are cleared allowing the pipeline to continue at the new instruction indicated by the branch 3 4 data hazards edit there are several main solutions and algorithms used to resolve data hazards insert a pipeline bubble whenever a read after write raw dependency is encountered guaranteed to increase latency or use out of order execution to potentially prevent the need for pipeline bubbles use operand forwarding to use data from later stages in the pipeline in the case of out of order execution the algorithm used can be scoreboarding in which case a pipeline bubble is needed only when there is no functional unit available the tomasulo algorithm which uses register renaming allowing continual issuing of instructions the task of removing data dependencies can be delegated to the compiler which can fill in an appropriate number of nop instructions between dependent instructions to ensure correct operation or re order instructions where possible operand forwarding edit main article operand forwarding examples edit in the following examples computed values are in bold while register numbers are not for example to write the value 3 to register 1 which already contains a 6 and then add 7 to register 1 and store the result in register 2 i e i0 r1 6 i1 r1 3 i2 r2 r1 7 10 following execution register 2 should contain the value 10 however if i1 write 3 to register 1 does not fully exit the pipeline before i2 starts executing it means that r1 does not contain the value 3 when i2 performs its addition in such an event i2 adds 7 to the old value of register 1 6 and so register 2 contains 13 instead i e i0 r1 6 i2 r2 r1 7 13 i1 r1 3 this error occurs because i2 reads register 1 before i1 has committed stored the result of its write operation to register 1 so when i2 is reading the contents of register 1 register 1 still contains 6 not 3 forwarding described below helps correct such errors by depending on the fact that the output of i1 which is 3 can be used by subsequent instructions before the value 3 is committed to stored in register 1 forwarding applied to the example means that there is no wait to commit store the output of i1 in register 1 in this example the output is 3 before making that output available to the subsequent instruction in this case i2 the effect is that i2 uses the correct the more recent value of register 1 the commit store was made immediately and not pipelined with forwarding enabled the instruction decode execution id ex stage of the pipeline now has two inputs the value read from the register specified in this example the value 6 from register 1 and the new value of register 1 in this example this value is 3 which is sent from the next stage instruction execute memory access ex mem added control logic is used to determine which input to use control hazards branch hazards edit to avoid control hazards microarchitectures can insert a pipeline bubble discussed above guaranteed to increase latency or use branch prediction and essentially make educated guesses about which instructions to insert in which case a pipeline bubble will only be needed in the case of an incorrect prediction in the event that a branch causes a pipeline bubble after incorrect instructions have entered the pipeline care must be taken to prevent any of the wrongly loaded instructions from having any effect on the processor state excluding energy wasted processing them before they were discovered to be loaded incorrectly other techniques edit memory latency is another factor that designers must attend to because the delay could reduce performance different types of memory have different accessing time to the memory thus by choosing a suitable type of memory designers can improve the performance of the pipelined data path 5 see also edit feed forward control register renaming data dependency control dependency hazard logic hazard pointer classic risc pipeline hazards speculative execution branch delay slot branch predication branch predictor race condition references edit patterson hennessy 2009 p 335 patterson hennessy 2009 pp 335 343 branch prediction schemes cs iastate edu 2001 04 06 retrieved 2014 07 19 data and control hazards classes soe ucsc edu 2004 02 23 retrieved 2014 07 19 cheng ching hwa 2012 12 27 design example of useful memory latency for developing a hazard preventive pipeline high performance embedded microprocessor vlsi design 2013 1 10 doi 10 1155 2013 425105 general edit patterson david hennessy john 2009 computer organization and design 4th ed morgan kaufmann isbn 978 0 12 374493 7 patterson david hennessy john 2011 computer architecture a quantitative approach 5th ed morgan kaufmann isbn 978 0 12 383872 8 shen john p lipasti mikko h 2013 2004 2 2 3 2 identication of pipeline hazards modern processor design fundamentals of superscalar processors waveland press pp 73 78 isbn 9781478610762 external links edit automatic pipelining from transactional datapath specifications pdf retrieved 23 july 2014 tulsen dean 18 january 2005 pipeline hazards pdf v t e processor technologies models abstract machine stored program computer finite state machine with datapath hierarchical deterministic finite automaton queue automaton cellular automaton quantum cellular automaton turing machine alternating turing machine universal post turing quantum nondeterministic turing machine probabilistic turing machine hypercomputation zeno machine belt machine stack machine register machines counter pointer random access random access stored program architecture microarchitecture von neumann harvard modified dataflow transport triggered cellular endianness memory access numa huma load store register memory cache hierarchy memory hierarchy virtual memory secondary storage heterogeneous fabric multiprocessing cognitive neuromorphic instruction set architectures types orthogonal instruction set cisc risc application specific edge trips vliw epic misc oisc nisc zisc visc architecture quantum computing comparison addressing modes instruction sets motorola 68000 series vax pdp 11 x86 arm stanford mips mips mips x power power powerpc power isa clipper architecture sparc superh dec alpha etrax cris m32r unicore itanium openrisc risc v microblaze lmc system 3x0 s 360 s 370 s 390 z architecture tilera isa visc architecture epiphany architecture others execution instruction pipelining pipeline stall operand forwarding classic risc pipeline hazards data dependency structural control false sharing out of order scoreboarding tomasulo s algorithm reservation station re order buffer register renaming wide issue speculative branch prediction memory dependence prediction parallelism level bit bit serial word instruction pipelining scalar superscalar task thread process data vector memory distributed multithreading temporal simultaneous hyperthreading simultaneous and heterogenous speculative preemptive cooperative flynn s taxonomy sisd simd array processing simt pipelined processing associative processing swar misd mimd spmd processor performance transistor count instructions per cycle ipc cycles per instruction cpi instructions per second ips floating point operations per second flops transactions per second tps synaptic updates per second sups performance per watt ppw cache performance metrics computer performance by orders of magnitude types central processing unit cpu graphics processing unit gpu gpgpu vector barrel stream tile processor coprocessor pal asic fpga fpoa cpld multi chip module mcm system in a package sip package on a package pop by application embedded system microprocessor microcontroller mobile ultra low voltage asip soft microprocessor systems on chip system on a chip soc multiprocessor mpsoc cypress psoc network on a chip noc hardware accelerators coprocessor ai accelerator graphics processing unit gpu image processor vision processing unit vpu physics processing unit ppu digital signal processor dsp tensor processing unit tpu secure cryptoprocessor network processor baseband processor word size 1 bit 4 bit 8 bit 12 bit 15 bit 16 bit 24 bit 32 bit 48 bit 64 bit 128 bit 256 bit 512 bit bit slicing others variable core count single core multi core manycore heterogeneous architecture components core cache cpu cache scratchpad memory data cache instruction cache replacement policies coherence bus clock rate clock signal fifo functional units arithmetic logic unit alu address generation unit agu floating point unit fpu memory management unit mmu load store unit translation lookaside buffer tlb branch predictor branch target predictor integrated memory controller imc memory management unit instruction decoder logic combinational sequential glue logic gate quantum array registers processor register status register stack register register file memory buffer memory address register program counter control unit hardwired control unit instruction unit data buffer write buffer microcode rom counter datapath multiplexer demultiplexer adder multiplier cpu binary decoder address decoder sum addressed decoder barrel shifter circuitry integrated circuit 3d mixed signal power management boolean digital analog quantum switch power management pmu apm acpi dynamic frequency scaling dynamic voltage scaling clock gating performance per watt ppw related history of general purpose cpus microprocessor chronology processor design digital electronics hardware security module semiconductor device fabrication tick tock model pin grid array chip carrier retrieved from https en wikipedia org w index php title hazard_ computer_architecture oldid 1362919561 control_hazards_ branch_hazards category instruction processing hidden categories articles with short description short description is different from wikidata articles needing additional references from january 2014 all articles needing additional references this page was last edited on 7 july 2026 at 00 24 utc page was rendered with parsoid text is available under the creative commons attribution sharealike 4 0 license additional terms may apply by using this site you agree to the terms of use and privacy policy wikipedia is a registered trademark of the wikimedia foundation inc a non profit organization privacy policy about wikipedia disclaimers contact wikipedia legal safety contacts code of conduct developers statistics cookie statement mobile view search search toggle the table of contents hazard computer architecture 7 languages add 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