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department of computer science and technology ctsrd skip to content access key help search advanced search a z contact us department of computer science and technology ctsrd project news bluespec extensible risc implementation beri capsicum capability hardware enhanced risc instructions cheri security oriented analysis of application programs soaap temporally enhanced security logic assertions tesla enhancing the satisfiability modulo theories experience smten publications open data posters and slides project members related ctsrd ctsrd rethinking the hardware software interface for security pis robert n m watson university of cambridge simon w moore university of cambridge peter sewell university of cambridge brooks davis sri international and peter neumann sri international september 2023 we have posted cheri isav9 which replaces cheri mips with cheri risc v as our primary reference architecture cheri mips is removed merged register files are always used tags are cleared in preference to exception throwing for non monotonic capability modification and ddc pcc no longer relocate memory accesses by default cheri risc v is substantially refined in preparation for standardisation the cheri x86 sketch is now substantially more detailed january 2022 arm has shipped its cheri enabled morello prototype processor soc and board read blog posts about this at arm and microsoft and our own thoughts at cambridge learn about the cheri architecture our technical report an introduction to cheri is a high level summary of our work on cheri architecture microarchitecture formal modeling and software clean slate trustworthy secure research and development ctsrd pronounced custard is a joint research project between sri international s computer science laboratory and the university of cambridge computer laboratory supported by darpa part of the darpa crash mrc and ssith programmes google and arm the project is revisiting the hardware software security interface for general purpose cpus to fundamentally improve security to this end we are integrating a hybrid capability model and continuous hardware assisted validation of security design principles with a commodity cpu isa and open source operating systems we are pursuing several new software hardware features as part of this research beri a open source hardware software research and teaching platform a 64 bit risc processor implemented in the high level bluespec hardware description language hdl along with compiler operating system and applications cheri capability hardware enhanced risc instructions hardware accelerated in process memory protection and sandboxing model based on a hybrid capability model tesla temporally enforced security logic assertions compiler generated runtime instrumentation continuously validating temporal security properties soaap security oriented analysis of application programs automated program analysis and transformation techniques to help software authors utilize capsicum and cheri features and smten smt based tools to support the formal verification of processor designs implemented in bluespec there is a strong interest throughout in judiciously applying formal methodology and bringing formally grounded techniques to mainstream hardware and software development this work has motivated the creation of the bluespec extensible risc implementation an open source platform for research into the hardware software interface with a bsd licensed operating system and toolchain based on freebsd and clang llvm we are using open source wherever possible to transition new technologies into mainstream use ctsrd builds on long past experience at both institutions in security and systems research including multics psos the newcastle dss separation kernels the darpa chats programme pvs sal yices lynuxworks the cap computer the mac framework multi threaded cpu design xen capsicum and mirageos news media the new scientist august 2018 uncrackable computer chips stop malicious bugs attacking your computer this article describes cheri and other projects focusing on more secure computer architectures the economist june 2014 hiding from big data robert watson explains how compartmentalised software designs could have mitigated heartbleed new york times october 2012 article on dr peter g neumann regarding clean slate research for security acm queue october 2012 interview with dr robert n m watson on research into the hardware software interface ieee spectrum december 2012 interview with dr robert n m watson on clean slate research for security 2010 2022 robert n m watson information provided by robert watson