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view source for digital visual interface wikipedia jump to content main menu main menu move to sidebar hide navigation main page contents current events random article about wikipedia contact us contribute help learn to edit community portal recent changes upload file special pages search search appearance donate create account log in personal tools donate create account log in view source for digital visual interface add languages article talk english read edit view history tools tools move to sidebar hide actions read edit view history general what links here related changes upload file page information get shortened url switch to legacy parser in other projects wikidata item appearance move to sidebar hide digital visual interface you do not have permission to edit this page for the following reason this ip address range has been globally blocked this does not affect your ability to read wikipedia pages most people who see this message have done nothing wrong some kinds of blocks restrict editing from specific service providers or telecom companies in response to recent abuse or vandalism and can sometimes affect other users who are unrelated to that abuse review the information below for assistance if you do not believe that you have done anything wrong this block affects editing on all wikimedia wikis the ip address or range 5 135 0 0 16 has been globally blocked by jon kolbert for the following reason s open proxy webhost visit the faq if you are affected this block will expire on 04 29 8 january 2027 your current ip address is 5 135 42 194 even while globally blocked you will usually still be able to edit pages on meta wiki if you believe you were blocked by mistake you can find additional information and instructions in the stewards block wizard other useful links global blocks help i have been blocked you can view and copy the source of this page specifications file adapter dvi to vga jpg thumb right a passive dvi to vga adapter this adapter will not work with a dvi d output it requires a dvi i or dvi a output to get the analog signal to a vga input even if the adapter looks like a dvi d a more expensive active adapter or converter is required to connect dvi d to vga digital minimum tmds clock frequency 25 175 mhz used for the mandatory low pixel format display mode vga resolution vga 640x480 60 hz maximum single link tmds clock frequency 165 mhz single link maximum gross bit rate including 8b 10b overhead 4 95 gbit s net bit rate subtracting 8b 10b overhead 3 96 gbit s dual link bit rates are twice that of single link at an identical clock frequency gross bit rate including 8b 10b overhead at a 165 mhz clock 9 90 gbit s net bit rate subtracting 8b 10b overhead 7 92 gbit s clocks above 165 mhz are allowed in dual link mode notetag and only used when total bandwidth requirement surpassing 330mhz tmds clock the specification only specifies first link to operate at above single link maximum in such scenario ref name dvi1 0 rp 2 2 2 bits per pixel 24 bits per pixel support is mandatory in all resolutions supported less than 24 bits per pixel is optional dual link optionally supports up to 48 bits per pixel if a depth greater than 24 bits per pixel is desired the least significant bits are sent on the second link pixels per tmds clock cycle 1 single link at 24 bits or less per pixel and dual link for 25 to 48 bits per pixel or 2 dual link at 24 bits or less per pixel example display modes single link sxga resx 1280 1024 85 hz with gtf blanking 159 mhz tmds clock fhd resx 1920 1080 60 hz with cvt rb blanking 139 mhz tmds clock uxga resx 1600 1200 60 hz with gtf blanking 161 mhz tmds clock wuxga resx 1920 1200 60 hz with cvt rb blanking 154 mhz tmds clock wqxga resx 2560 1600 30 hz with cvt rb blanking 132 mhz tmds clock example display modes dual link qxga resx 2048 1536 72 hz with cvt blanking 2 pixels per 163 mhz tmds clock fhd resx 1920 1080 144 hz citation needed date may 2026 wuxga resx 1920 1200 120 hz with cvt rb blanking 2 pixels per 154 mhz tmds clock wqxga resx 2560 1600 60 hz with cvt rb blanking 2 pixels per 135 mhz tmds clock wquxga resx 3840 2400 30 hz with cvt rb blanking 2 pixels per 146 mhz tmds clock generalized timing formula gtf is a vesa standard which can easily be calculated with the linux gtf utility coordinated video timings reduced blanking cvt rb is a vesa standard which offers reduced horizontal and vertical blanking for non crt based displays ref cite news url https www nvidia com object advanced_timings html title advanced timing and cea eia 861b timings publisher nvidia access date 2008 06 18 ref digital data encoding one of the purposes of dvi stream encoding is to provide a dc balanced output that reduces decoding errors this goal is achieved by using 10 bit symbols for 8 bit or less characters and using the extra bits for the dc balancing like other ways of transmitting video there are two different regions the active region where pixel data is sent and the control region where synchronization signals are sent the active region is encoded using transition minimized differential signaling where the control region is encoded with a fixed 8b 10b encoding as the two schemes yield different 10 bit symbols a receiver can fully differentiate between active and control regions when dvi was designed most computer monitors were still of the cathode ray tube type that require analog video synchronization signals the timing of the digital synchronization signals matches the equivalent analog ones so the process of transforming dvi to and from an analog signal does not require extra high speed memory expensive at the time high bandwidth digital content protection hdcp is an extra layer that transforms the 10 bit symbols before transmitting only after correct authorization can the receiver undo the hdcp encryption control regions are not encrypted in order to let the receiver know when the active region starts clock and data relationship dvi provide one tmds clock pair and three data pairs in single link mode or six data pairs in dual link mode tmds data pairs operate at a gross bit rate that is 10 times the frequency of the tmds clock in each tmds clock period there is a 10 bit symbol per tmds data pair representing 8 bits of pixel color in single link mode each set of three 10 bit symbols represents one 24 bit pixel while in dual link mode each set of six 10 bit symbols either represents two 24 bit pixels or one pixel of up to 48 bit color depth the specification document allows the data and the clock to not be aligned however as the ratio between the tmds clock and gross bit rate per tmds pair is fixed at 1 10 the unknown alignment is kept over time the receiver must recover the bits on the stream using any of the techniques of clock recovery clock data recovery to find the correct symbol boundary the dvi specification allows the tmds clock to vary between 25 and 165 mhz this 1 6 6 ratio can make clock recovery difficult as phase locked loop s if used need to work over a large frequency range one benefit of dvi over other interfaces is that it is relatively straightforward to transform the signal from the digital domain into the analog domain using a video digital to analog converter dac as both clock and synchronization signals are transmitted fixed frequency interfaces like displayport need to reconstruct the clock from the transmitted data display power management the dvi specification includes signaling for reducing power consumption similar to the analog vesa display power management signaling dpms standard a connected device can turn a monitor off when the connected device is powered down or programmatically if the display controller of the device supports it devices with this capability can also attain energy star certification analog the analog section of the dvi specification document is brief and points to other specifications like vesa vsis ref video signal standard vsis version 1 rev 2 available for purchase at http www vesa org ref for electrical characteristics and generalized timing formula gtfs for timing information the motivation for including analog is to keep compatibility with the previous vga connector vga cables and connectors vga pins for hsync vsync and three video channels are available in both dvi i or dvi a but not dvi d connectors and are electrically compatible while pins for ddc clock and data and 5 v power and ground are kept in all dvi connectors thus a passive adapter can interface between dvi i or dvi a but not dvi d and vga connectors return to digital visual interface retrieved from https en wikipedia org wiki digital_visual_interface privacy policy about wikipedia disclaimers contact wikipedia legal safety contacts code of conduct developers statistics cookie statement mobile view search search view source for digital visual interface add languages add topic