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Text of the page (random words):
pros and cons toggle pros and cons subsection 3 1 advantages 3 2 disadvantages 4 applications 5 variations toggle variations subsection 5 1 original definition 5 1 1 an991 5 2 timing variations 5 3 transmission size 5 4 no slave select 5 5 connectors 5 6 flow control 5 7 safespi 5 8 high reliability modifications 5 9 intelligent spi controllers 5 10 three wire 5 11 bit width extensions 5 11 1 dual spi 5 11 2 quad spi 5 11 3 qpi sqi 5 12 double data rate 5 13 sgpio 5 14 intel s enhanced serial peripheral interface 6 interoperability with other standards toggle interoperability with other standards subsection 6 1 microwire 6 2 microwire plus 6 3 jtag 7 development tools toggle development tools subsection 7 1 single board computers 7 2 usb to spi adapters 7 3 protocol analyzers 7 3 1 oscilloscopes 8 alternative terminology 9 see also 10 notes 11 references 12 external links toggle the table of contents serial peripheral interface 30 languages العربية català čeština dansk deutsch español eesti euskara فارسی suomi français עברית magyar italiano 日本語 한국어 nederlands norsk bokmål polski português română русский simple english slovenčina slovenščina svenska türkçe українська tiếng việt 中文 edit links article talk english read edit view history tools tools move to sidebar hide actions read edit view history general what links here related changes upload file permanent link page information cite this page get shortened url switch to new parser parsoid print export download as pdf printable version in other projects wikimedia commons wikidata item appearance move to sidebar hide from wikipedia the free encyclopedia synchronous serial communication interface this article may need to be rewritten to comply with wikipedia s quality standards as it reads like a guide or textbook relevant discussion may be found on the talk page you can help the talk page may contain suggestions march 2021 serial peripheral interface spi type serial communication bus production history designer motorola designed around early 1980s note 1 manufacturer various daisy chain depends on devices connector unspecified electrical max voltage unspecified max current unspecified data width 1 bit bidirectional max devices multidrop limited by slave selects daisy chaining unlimited protocol full duplex serial pinout mosi master out slave in miso master in slave out sclk serial clock ss slave select one or more pins may have alternative names serial peripheral interface spi is a de facto standard with many variants for synchronous serial communication used primarily in embedded systems for short distance wired communication between integrated circuits spi follows a master slave architecture 1 where a device variously called master leader controller main orchestrates communication with one or more devices variously called slave follower target sub by driving the clock and chip select signals as there is no formal standard some manufacturers introduce devices with the ability to change their roles on the fly motorola s original specification from the early 1980s uses four logic signals aka lines or wires to support full duplex communication it is sometimes called a four wire serial bus to contrast with three wire variants which are half duplex and with the two wire i²c and 1 wire serial buses typical applications include interfacing microcontrollers with peripheral chips for secure digital cards liquid crystal displays analog to digital and digital to analog converters flash and eeprom memory and various communication chips although spi is a synchronous serial interface 2 it is different from synchronous serial interface ssi ssi employs differential signaling and provides only a single simplex communication channel operation edit single master to single slave basic spi wiring commonly spi has four logic signals variations may use different names or have different signals abbr name description ss slave select active low chip select signal from master to enable communication with a specific slave device sclk serial clock clock signal from master mosi master out slave in serial data output from master miso master in slave out serial data output from slave mosi on a master outputs to mosi on a slave miso on a slave outputs to miso on a master each device internally uses a shift register for serial communication which together forms an inter chip circular buffer to support multidrop bus slave devices should use tri state outputs so their miso signal becomes high impedance electrically disconnected when the device is not selected slaves without tri state outputs cannot share a miso line with other slaves without using an external tri state buffer data transmission edit a typical hardware setup using two shift registers to form an inter chip circular buffer serial peripheral interface animation this animation shows a scenario where the master sends 8 bit data and simultaneously reads 16 bit data from the slave the lower boxes represent the device s memories to begin communication the spi master first selects the device it wants to communicate with by pulling its ss low the bar above ss indicates it is an active low signal so a low voltage means selected while a high voltage means not selected if a waiting period is required such as for an analog to digital conversion the master must wait for at least that period of time before issuing clock cycles note 2 during each spi clock cycle full duplex transmission of a single bit occurs the master sends a bit on the mosi line while the slave sends a bit on the miso line and then each reads their corresponding incoming bit this sequence is maintained even when only one directional data transfer is intended transmission using a single slave involves one shift register in the master and one shift register in the slave both of some given word size e g 8 bits the transmissions often consist of eight bit words but other word sizes are also common for example sixteen bit words for touch screen controllers or audio codecs such as the tsc2101 by texas instruments or twelve bit words for many digital to analog or analog to digital converters data is usually shifted out with the most significant bit msb first but the original specification has a lsbfe lsb first enable to control whether data is transferred least lsb or most significant bit msb first on the clock edge both master and slave shift out a bit to its counterpart on the next clock edge each receiver samples the transmitted bit and stores it in the shift register as the new least significant bit after all bits have been shifted out and in the master and slave have exchanged register values if more data needs to be exchanged the shift registers are reloaded and the process repeats transmission may continue for any number of clock cycles when complete the master stops toggling the clock signal and typically deselects the slave if a single slave device is used its ss pin may be fixed to logic low if the slave permits it with multiple slave devices a multidrop configuration requires an independent ss signal from the master for each slave device while a daisy chain configuration only requires one ss signal every slave on the bus that has not been selected should disregard the input clock and mosi signals and to prevent contention on miso non selected slaves must use tristate output slaves that are not already tristate will need external tristate buffers to ensure this 3 clock polarity and phase edit in addition to setting the clock frequency the master must also configure the clock polarity and phase with respect to the data motorola 4 5 named these two options as cpol and cpha for c lock pol arity and c lock pha se respectively a convention most vendors have also adopted spi timing diagram for both clock polarities and phases data bits output on blue lines if cpha 0 or on red lines if cpha 1 and sample on opposite colored lines numbers identify data bits z indicates high impedance the spi timing diagram shown is further described below cpol represents the polarity of the clock polarities can be converted with a simple inverter sclk cpol 0 is a clock which idles at the logical low voltage sclk cpol 1 is a clock which idles at the logical high voltage cpha represents the phase of each data bit s transmission cycle relative to sclk for cpha 0 the first data bit is output immediately when ss activates subsequent bits are output when sclk transitions to its idle voltage level sampling occurs when sclk transitions from its idle voltage level for cpha 1 the first data bit is output on sclk s first clock edge after ss activates subsequent bits are output when sclk transitions from its idle voltage level sampling occurs when sclk transitions to its idle voltage level conversion between these two phases is non trivial mosi and miso signals are usually stable at their reception points for the half cycle until the next bit s transmission cycle starts so spi master and slave devices may sample data at different points in that half cycle for flexibility despite the original specification mode numbers edit the combinations of polarity and phases are referred to by these spi mode numbers with cpol as the high order bit and cpha as the low order bit spi mode clock polarity cpol clock phase cpha data is shifted out on data is sampled on 0 0 0 falling sclk and when ss activates rising sclk 1 0 1 rising sclk falling sclk 2 1 0 rising sclk and when ss activates falling sclk 3 1 1 falling sclk rising sclk notes another commonly used notation represents the mode as a cpol cpha tuple e g the value 0 1 would indicate cpol 0 and cpha 1 in full duplex operation the master device could transmit and receive with different modes for instance it could transmit in mode 0 and be receiving in mode 1 at the same time different vendors may use different naming schemes like cke for clock edge or ncpha for the inversion of cpha valid communications edit some slave devices are designed to ignore any spi communications in which the number of clock pulses is greater than specified others do not care ignoring extra inputs and continuing to shift the same output bit it is common for different devices to use spi communications with different lengths as for example when spi is used to access an ic s scan chain by issuing a command word of one size perhaps 32 bits and then getting a response of a different size perhaps 153 bits one for each pin in that scan chain interrupts edit interrupts are outside the scope of spi their usage is neither forbidden nor specified and so may be implemented optionally from master to slave edit microcontrollers configured as slave devices may have hardware support for generating interrupt signals to themselves when data words are received or overflow occurs in a receive fifo buffer 6 and may also set up an interrupt routine when their slave select input line is pulled low or high from slave to master edit spi slaves sometimes use an out of band signal another wire to send an interrupt signal to a master examples include pen down interrupts from touchscreen sensors thermal limit alerts from temperature sensors alarms issued by real time clock chips sdio note 3 and audio jack insertions for an audio codec interrupts to master may also be faked by using polling similarly to usb 1 1 and 2 0 bus topologies edit though the previous operation section focused on a basic interface with a single slave spi can instead communicate with multiple slaves using multidrop daisy chain or expander configurations multidrop configuration edit multidrop spi bus in the multidrop bus configuration each slave has its own ss and the master selects only one at a time miso sclk and mosi are each shared by all devices this is the way spi is normally used since the miso pins of the slaves are connected together they are required to be tri state pins high low or high impedance where the high impedance output must be applied when the slave is not selected slave devices not supporting tri state may be used in multidrop configuration by adding a tri state buffer chip controlled by its ss signal 3 since only a single signal line needs to be tristated per slave one typical standard logic chip that contains four tristate buffers with independent gate inputs can be used to interface up to four slave devices to an spi bus caveat all ss signals should start high to indicate no slaves are selected before sending initialization messages to any slave so other uninitialized slaves ignore messages not addressed to them this is a concern if the master uses general purpose input output gpio pins which may default to an undefined state for ss and if the master uses separate software libraries to initialize each device one solution is to configure all gpios used for ss to output a high voltage for all slaves before running initialization code from any of those software libraries another solution is to add a pull up resistor on each ss to ensure that all ss signals are initially high 3 daisy chain configuration edit daisy chained spi some products that implement spi may be connected in a daisy chain configuration where the first slave s output is connected to the second slave s input and so on with subsequent slaves until the final slave whose output is connected back to the master s input this effectively merges the individual communication shift registers of each slave to form a single larger combined shift register that shifts data through the chain this configuration only requires a single ss line from the master rather than a separate ss line for each slave 7 in addition to using spi specific slaves daisy chained spi can include discrete shift registers for more pins of inputs e g using the parallel in serial out 74 xx165 8 or outputs e g using the serial in parallel out 74 xx595 9 chained indefinitely other applications that can potentially interoperate with daisy chained spi include sgpio jtag 10 and i 2 c expander configurations edit expander configurations use spi controlled addressing units e g binary decoders demultiplexers or shift registers to add chip selects for example one ss can be used for transmitting to a spi controlled demultiplexer an index number controlling its select signals while another ss is routed through that demultiplexer according to that index to select the desired slave 11 pros and cons edit advantages edit full duplex communication in the default version of this protocol push pull drivers as opposed to open drain provide relatively good signal integrity and high speed higher throughput than i²c or smbus spi s protocol has no maximum clock speed however individual devices specify acceptable clock frequencies wiring and electronics limit frequency complete protocol flexibility for the bits transferred not limited to 8 bit symbols arbitrary choice of message size content and purpose simple hardware and interfacing hardware implementation for slaves only requires a selectable shift register slaves use the master ...