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example loop nest optimization however with register renaming most compiler register assignments are reallocated dynamically by hardware at runtime into a register bank allowing the cpu to break false data dependencies and thus easing pipeline hazards register files sometimes also have hierarchy the cray 1 circa 1976 had eight address a and eight scalar data s registers that were generally usable there was also a set of 64 address b and 64 scalar data t registers that took longer to access but were faster than main memory the b and t registers were provided because the cray 1 did not have a data cache the cray 1 did however have an instruction cache multi core chips edit when considering a chip with multiple cores there is a question of whether the caches should be shared or local to each core implementing shared cache inevitably introduces more wiring and complexity but then having one cache per chip rather than core greatly reduces the amount of space needed and thus one can include a larger cache typically sharing the l1 cache is undesirable because the resulting increase in latency would make each core run considerably slower than a single core chip however for the highest level cache usually l3 the last one called before accessing memory having a global cache is desirable for several reasons such as allowing a single core to use the whole cache reducing data redundancy by making it possible for different processes or threads to share cached data and reducing the complexity of utilized cache coherency protocols 54 for example an eight core chip with three levels may include an l1 cache for each core one intermediate l2 cache for each pair of cores and one l3 cache shared between all cores a shared highest level cache usually l3 called before accessing memory is usually referred to as a last level cache llc 55 additional techniques are used for increasing the level of parallelism when llc is shared between multiple cores including slicing it into multiple pieces which are addressing certain ranges of memory addresses and can be accessed independently 8 56 separate versus unified edit in a separate cache structure instructions and data are cached separately meaning that a cache line is used to cache either instructions or data but not both various benefits have been demonstrated with separate data and instruction translation lookaside buffers 57 in a unified structure this constraint is not present and cache lines can be used to cache both instructions and data exclusive versus inclusive edit multi level caches introduce new design decisions for instance in some processors all data in the l1 cache must also be somewhere in the l2 cache these caches are called strictly inclusive other processors like the amd athlon have exclusive caches data are guaranteed to be in at most one of the l1 and l2 caches never in both still other processors like the intel pentium ii iii and 4 do not require that data in the l1 cache also reside in the l2 cache although it may often do so there is no universally accepted name for this intermediate policy 58 59 two common names are non exclusive and partially inclusive the advantage of exclusive caches is that they store more data this advantage is larger when the exclusive l1 cache is comparable to the l2 cache and diminishes if the l2 cache is many times larger than the l1 cache when the l1 misses and the l2 hits on an access the hitting cache line in the l2 is exchanged with a line in the l1 this exchange is quite a bit more work than just copying a line from l2 to l1 which is what an inclusive cache does 59 one advantage of strictly inclusive caches is that when external devices or other processors in a multiprocessor system wish to remove a cache line from the processor they need only have the processor check the l2 cache in cache hierarchies which do not enforce inclusion the l1 cache must be checked as well as a drawback there is a correlation between the associativities of l1 and l2 caches if the l2 cache does not have at least as many ways as all l1 caches together the effective associativity of the l1 caches is restricted another disadvantage of inclusive cache is that whenever there is an eviction in l2 cache the possibly corresponding lines in l1 also have to get evicted in order to maintain inclusiveness this is quite a bit of work and would result in a higher l1 miss rate 59 another advantage of inclusive caches is that the larger cache can use larger cache lines which reduces the size of the secondary cache tags exclusive caches require both caches to have the same size cache lines so that cache lines can be swapped on a l1 miss l2 hit if the secondary cache is an order of magnitude larger than the primary and the cache data are an order of magnitude larger than the cache tags this tag area saved can be comparable to the incremental area needed to store the l1 cache data in the l2 60 scratchpad memory edit main article scratchpad memory scratchpad memory spm also known as scratchpad scratchpad ram or local store in computer terminology is a high speed internal memory used for temporary storage of calculations data and other work in progress example the k8 edit to illustrate both specialization and multi level caching here is the cache hierarchy of the k8 core in the amd athlon 64 cpu 61 cache hierarchy of the k8 core in the amd athlon 64 cpu the k8 has four specialized caches an instruction cache an instruction tlb a data tlb and a data cache each of these caches is specialized the instruction cache keeps copies of 64 byte lines of memory and fetches 16 bytes each cycle each byte in this cache is stored in ten bits rather than eight with the extra bits marking the boundaries of instructions this is an example of predecoding the cache has only parity protection rather than ecc because parity is smaller and any damaged data can be replaced by fresh data fetched from memory which always has an up to date copy of instructions the instruction tlb keeps copies of page table entries ptes each cycle s instruction fetch has its virtual address translated through this tlb into a physical address each entry is either four or eight bytes in memory because the k8 has a variable page size each of the tlbs is split into two sections one to keep ptes that map 4 kib pages and one to keep ptes that map 4 mib or 2 mib pages the split allows the fully associative match circuitry in each section to be simpler the operating system maps different sections of the virtual address space with different size ptes the data tlb has two copies which keep identical entries the two copies allow two data accesses per cycle to translate virtual addresses to physical addresses like the instruction tlb this tlb is split into two kinds of entries the data cache keeps copies of 64 byte lines of memory it is split into 8 banks each storing 8 kib of data and can fetch two 8 byte data each cycle so long as those data are in different banks there are two copies of the tags because each 64 byte line is spread among all eight banks each tag copy handles one of the two accesses per cycle the k8 also has multiple level caches there are second level instruction and data tlbs which store only ptes mapping 4 kib both instruction and data caches and the various tlbs can fill from the large unified l2 cache this cache is exclusive to both the l1 instruction and data caches which means that any 8 byte line can only be in one of the l1 instruction cache the l1 data cache or the l2 cache it is however possible for a line in the data cache to have a pte which is also in one of the tlbs the operating system is responsible for keeping the tlbs coherent by flushing portions of them when the page tables in memory are updated the k8 also caches information that is never stored in memory prediction information these caches are not shown in the above diagram as is usual for this class of cpu the k8 has fairly complex branch prediction with tables that help predict whether branches are taken and other tables which predict the targets of branches and jumps some of this information is associated with instructions in both the level 1 instruction cache and the unified secondary cache the k8 uses an interesting trick to store prediction information with instructions in the secondary cache lines in the secondary cache are protected from accidental data corruption e g by an alpha particle strike by either ecc or parity depending on whether those lines were evicted from the data or instruction primary caches since the parity code takes fewer bits than the ecc code lines from the instruction cache have a few spare bits these bits are used to cache branch prediction information associated with those instructions the net result is that the branch predictor has a larger effective history table and so has better accuracy more hierarchies edit other processors have other kinds of predictors e g the store to load bypass predictor in the dec alpha 21264 these predictors are caches in that they store information that is costly to compute some of the terminology used when discussing predictors is the same as that for caches one speaks of a hit in a branch predictor but predictors are not generally thought of as part of the cache hierarchy the k8 keeps the instruction and data caches coherent in hardware which means that a store into an instruction closely following the store instruction will change that following instruction other processors like those in the alpha and mips family have relied on software to keep the instruction cache coherent stores are not guaranteed to show up in the instruction stream until a program calls an operating system facility to ensure coherency tag ram edit tag ram on board of a intel pentium iii in computer engineering a tag ram is used to specify which of the possible memory locations is currently stored in a cpu cache 62 63 for a simple direct mapped design fast sram can be used higher associative caches usually employ content addressable memory implementation edit main article cache algorithms cache reads are the most common cpu operation that takes more than a single cycle program execution time tends to be very sensitive to the latency of a level 1 data cache hit a great deal of design effort and often power and silicon area are expended making the caches as fast as possible the simplest cache is a virtually indexed direct mapped cache the virtual address is calculated with an adder the relevant portion of the address extracted and used to index an sram which returns the loaded data the data are byte aligned in a byte shifter and from there are bypassed to the next operation there is no need for any tag checking in the inner loop in fact the tags need not even be read later in the pipeline but before the load instruction is retired the tag for the loaded data must be read and checked against the virtual address to make sure there was a cache hit on a miss the cache is updated with the requested cache line and the pipeline is restarted an associative cache is more complicated because some form of tag must be read to determine which entry of the cache to select an n way set associative level 1 cache usually reads all n possible tags and n data in parallel and then chooses the data associated with the matching tag level 2 caches sometimes save power by reading the tags first so that only one data element is read from the data sram read path for a 2 way associative cache the adjacent diagram is intended to clarify the manner in which the various fields of the address are used address bit 31 is most significant bit 0 is least significant the diagram shows the srams indexing and multiplexing for a 4 kib 2 way set associative virtually indexed and virtually tagged cache with 64 byte b lines a 32 bit read width and 32 bit virtual address because the cache is 4 kib and has 64 b lines there are just 64 lines in the cache and we read two at a time from a tag sram which has 32 rows each with a pair of 21 bit tags although any function of virtual address bits 31 through 6 could be used to index the tag and data srams it is simplest to use the least significant bits similarly because the cache is 4 kib and has a 4 b read path and reads two ways for each access the data sram is 512 rows by 8 bytes wide a more modern cache might be 16 kib 4 way set associative virtually indexed virtually hinted and physically tagged with 32 b lines 32 bit read width and 36 bit physical addresses the read path recurrence for such a cache looks very similar to the path above instead of tags virtual hints are read and matched against a subset of the virtual address later on in the pipeline the virtual address is translated into a physical address by the tlb and the physical tag is read just one as the virtual hint supplies which way of the cache to read finally the physical address is compared to the physical tag to determine if a hit has occurred some sparc designs have improved the speed of their l1 caches by a few gate delays by collapsing the virtual address adder into the sram decoders see sum addressed decoder history edit the early history of cache technology is closely tied to the invention and use of virtual memory citation needed because of scarcity and cost of semi conductor memories early mainframe computers in the 1960s used a complex hierarchy of physical memory mapped onto a flat virtual memory space used by programs the memory technologies would span semi conductor magnetic core drum and disc virtual memory seen and used by programs would be flat and caching would be used to fetch data and instructions into the fastest memory ahead of processor access extensive studies were done to optimize the cache sizes optimal values were found to depend greatly on the programming language used with algol needing the smallest and fortran and cobol needing the largest cache sizes disputed discuss in the early days of microcomputer technology memory access was only slightly slower than register access but since the 1980s 64 the performance gap between processor and memory has been growing microprocessors have advanced much faster than memory especially in terms of their operating frequency so memory became a performance bottleneck while it was technically possible to have all the main memory as fast as the cpu a more economically viable path has been taken use plenty of low speed memory but also introduce a small high speed cache memory to alleviate the performance gap this provided an order of magnitude more capacity for the same price with only a slightly reduced combined performance first tlb implementations edit the first documented uses of a tlb were on the ge 645 65 and the ibm 360 67 66 both of which used an associative memory as a tlb first instruction cache edit the first documented use of an instruction cache was on the cdc 6600 67 first data cache edit the first documented use of a data cache was on the ibm system 360 model 85 68 in 68k...