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coherent accelerator processor interface wikipedia jump to content main menu main menu move to sidebar hide navigation main page contents current events random article about wikipedia contact us contribute help learn to edit community portal recent changes upload file special pages search search appearance donate create account log in personal tools donate create account log in contents move to sidebar hide top 1 history 2 implementation toggle implementation subsection 2 1 capi 2 1 1 capi 2 1 2 capi 2 2 2 opencapi 2 2 1 opencapi 3 2 2 2 opencapi 4 2 2 3 omi 3 see also 4 references 5 external links toggle the table of contents coherent accelerator processor interface 2 languages català deutsch edit links article talk english read edit view history tools tools move to sidebar hide actions read edit view history general what links here related changes upload file permanent link page information cite this page get shortened url switch to legacy parser print export download as pdf printable version in other projects wikidata item appearance move to sidebar hide from wikipedia the free encyclopedia processor expansion bus standard coherent accelerator processor interface year created 2014 12 years ago 2014 created by ibm coherent accelerator processor interface capi is a high speed processor expansion bus standard for use in large data center computers initially designed to be layered on top of pci express for directly connecting central processing units cpus to external accelerators like graphics processing units gpus asics fpgas or fast storage 1 2 it offers low latency high speed direct memory access connectivity between devices of different instruction set architectures history edit the performance scaling traditionally associated with moore s law dating back to 1965 began to taper off around 2004 as both intel s prescott architecture and ibm s cell processor pushed toward a 4 ghz operating frequency here both projects ran into a thermal scaling wall whereby heat extraction problems associated with further increases in operating frequency largely outweighed gains from shorter cycle times over the decade that followed few commercial cpu products exceeded 4 ghz with the majority of performance improvements now coming from incrementally improved microarchitectures better systems integration and higher compute density this largely in the form of packing a larger numbers of independent cores onto the same die often at the expense of peak operating frequency intel s 24 core xeon e7 8890 from june 2016 has a base operating frequency of just 2 2 ghz so as to operate within the constraints of a single socket 165 w power consumption and cooling budget where large performance gains have been realized it was often associated with increasingly specialized compute units such as gpu units added to the processor die or external gpu or fpga based accelerators in many applications accelerators struggle with limitations of the interconnect s performance bandwidth and latency or with limitations due to the interconnect s architecture such as lacking memory coherence especially in the datacenter improving the interconnect became paramount in moving toward a heterogeneous architecture in which hardware becomes increasingly tailored to specific compute workloads capi was developed to enable computers to more easily and efficiently attach specialized accelerators memory intensive and computation intensive works like matrix multiplications for deep neural networks can be offloaded into capi supported platforms 3 it was designed by ibm for use in its power8 based systems which came to market in 2014 at the same time ibm and several other companies founded the openpower foundation to build an ecosystem around power based technologies including capi in october 2016 several openpower partners formed the opencapi consortium together with gpu and cpu designer amd and systems designers dell emc and hewlett packard enterprise to spread the technology beyond the scope of openpower and ibm 4 on august 1 2022 opencapi specifications and assets were transferred to the compute express link cxl consortium 5 implementation edit capi edit capi is implemented as a functional unit inside the cpu called the coherent accelerator processor proxy capp with a corresponding unit on the accelerator called the power service layer psl the capp and psl units acts like a cache directory so the attached device and the cpu can share the same coherent memory space and the accelerator becomes an accelerator function unit afu a peer to other functional units integrated in the cpu 6 7 since the cpu and afu share the same memory space low latency and high speeds can be achieved since the cpu doesn t have to do memory translations and memory shuffling between the cpu s main memory and the accelerator s memory spaces an application can make use of the accelerator without specific device drivers as everything is enabled by a general capi kernel extension in the host operating system the cpu and psl can read and write directly to each other s memories and registers as demanded by the application capi edit capi is layered on top of pcie gen 3 using 16 pcie lanes and is an additional functionality for the pcie slots on capi enabled systems usually there are designated capi enabled pcie slots on such machines since there is only one capp per power8 processor the number of possible capi units are determined by the number of power8 processors regardless of how many pcie slots there are in certain power8 systems ibm makes use of dual chip modules thus doubling the capi capacity per processor socket traditional transactions between a pcie device and a cpu can take around 20 000 operations whereas a capi attached device will only use around 500 significantly reducing latency and effectively increasing bandwidth due to decreased operations overhead 7 the total bandwidth of a capi port is determined by the underlying pcie 3 0 x16 technology peaking at ca 16 gb s bidirectional 8 capi 2 edit capi 2 is an incremental evolution of the technology introduced with ibm power9 processor 8 it runs on top of pcie gen 4 that effectively doubles the performance to 32 gb s it also introduces some new features like support for dma and atomics from the accelerator opencapi edit the technology behind opencapi is governed by the opencapi consortium founded in october 2016 by amd google ibm mellanox and micron together with partners nvidia hewlett packard enterprise dell emc and xilinx 9 opencapi 3 edit opencapi formerly new capi or capi 3 0 is not layered on top of pcie and will therefore not use pcie slots in ibm s cpu power9 it will use the bluelink 25g i o facility that it shares with nvlink 2 0 peaking at 50 gb s 10 opencapi doesn t need the psl unit required for capi 1 and 2 in the accelerator as it s not layered on top of pcie but uses its own transaction protocol 11 opencapi 4 edit planned for future chip after the general availability of power9 12 omi edit opencapi memory interface omi is a serial attached ram technology based on opencapi providing low latency high bandwidth connection for main memory omi uses a controller chip on the memory modules that allows for technology agnostic approach to what is used on the modules be it ddr4 ddr5 hbm or storage class non volatile ram an omi based cpu can therefore change ram type by changing the memory modules a serial connection uses less floorspace for the interface on the cpu die therefore potentially allowing more of them compared to using common ddr memory omi is implemented in ibm s power10 cpu which has 8 omi memory controllers on chip allowing for 4 tb ram and 410 gb s memory bandwidth per processor these ddimms differential dynamic memory module includes an omi controller and memory buffer and can address individual memory chips for fault tolerance and redundancy purposes microchip technology manufactures the omi controller on the ddimms their smc 1000 opencapi memory is described as the next progression in the market adopting serial attached memory 13 see also edit legacy abandoned intel quickpath interconnect qpi rapidio hypertransport legacy updated pci express pcie nvlink infinity fabric evolution of hypertransport contemporary compute express link cxl gen z ccix references edit agam shah 17 december 2014 ibm s new power8 doubles performance of watson chip pc world archived from the original on 1 february 2018 retrieved 17 december 2014 ibm power8 processor detailed features 22nm design with 12 cores 96 mb edram l3 cache and 4 ghz clock speed wccftech 27 august 2013 retrieved 17 december 2014 md syadus sefat semih aslan jeffrey w kellington apan qasem 2019 10 03 accelerating hotspots in deep neural networks on a capi based fpga 2019 ieee 21st international conference on high performance computing and communications ieee 17th international conference on smart city ieee 5th international conference on data science and systems hpcc smart city dss ieee pp 248 256 doi 10 1109 hpcc smartcity dss 2019 00048 isbn 978 1 7281 2058 4 s2cid 203656070 cite book cs1 maint multiple names authors list link opencapi unveiled amd ibm google xilinx micron and mellanox join forces in the heterogenous computing era cxl consortium and opencapi consortium sign letter of intent to transfer opencapi specifications to cxl coherent accelerator processor interface capi for power8 systems white paper 1 2 reconfigurable accelerators for big data and cloud raw 2016 1 2 opening up the server bus for coherent acceleration tech leaders unite to enable new cloud datacenter server designs for big data machine learning analytics and other emerging workloads big blue aims for the sky with power9 opencapi takes on pcie vows 10x improvement stuecheli jeff 26 january 2017 webinar power9 video recording slides aix virtual user group slides pdf aix vug page has links to slides and video patrick kennedy august 5 2019 microchip smc 1000 for the serial attached memory future servethehome external links edit opencapi consortium open memory interface omi v t e technical and de facto standards for wired computer buses general system bus front side bus back side bus daisy chain control bus address bus bus contention bus mastering network on a chip plug and play double data rate quad data rate list of bus bandwidths standards ss 50 bus s 100 bus multibus unibus vaxbi mbus std bus smbus q bus europe card bus isa stebus zorro ii zorro iii camac fastbus lpc hp precision bus eisa vme vxi vxs vpx nubus turbochannel mca sbus vlb hp gsc bus infiniband ethernet upa pci pci extended pci x pxi pci express pcie agp compute express link cxl direct media interface dmi rapidio intel quickpath interconnect nvlink hypertransport infinity fabric intel ultra path interconnect coherent accelerator processor interface capi spacewire storage st 506 esdi sdi ipi smd floppy connector parallel ata pata bus and tag dssi hippi serial ata sata scsi parallel sas escon fibre channel ssa satae pci express via ahci or nvme logical device interface peripheral apple desktop bus atari sio dcb commodore bus hp il hil midi rs 232 rs 422 rs 423 rs 485 lightning dmx512 a ieee 488 gpib ieee 1284 parallel port ieee 1394 firewire uni o 1 wire i 2 c access bus pmbus smbus i3c spi d²b parallel scsi profibus usb camera link external pcie thunderbolt can bus audio adat lightpipe aes3 intel hd audio i 2 s madi mcasp s pdif toslink portable pc card expresscard embedded multidrop bus coreconnect amba axi wishbone slimbus interfaces are listed by their speed in the roughly ascending order so the interface at the end of each section should be the fastest category retrieved from https en wikipedia org w index php title coherent_accelerator_processor_interface oldid 1345328166 categories peripheral component interconnect serial buses motherboard expansion slot hidden categories articles with short description short description is different from wikidata cs1 maint multiple names authors list this page was last edited on 25 march 2026 at 14 58 utc page was rendered with parsoid text is available under the creative commons attribution sharealike 4 0 license additional terms may apply by using this site you agree to the terms of use and privacy policy wikipedia is a registered trademark of the wikimedia foundation inc a non profit organization privacy policy about wikipedia disclaimers contact wikipedia legal safety contacts code of conduct developers statistics cookie statement mobile view search search toggle the table of contents coherent accelerator processor interface 2 languages add topic