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data dependency wikipedia jump to content main menu main menu move to sidebar hide navigation main page contents current events random article about wikipedia contact us contribute help learn to edit community portal recent changes upload file special pages search search appearance donate create account log in personal tools donate create account log in contents move to sidebar hide top 1 description 2 types toggle types subsection 2 1 data hazards 2 1 1 read after write raw 2 1 1 1 example 2 1 2 write after read war 2 1 2 1 example 2 1 3 write after write waw 2 1 3 1 example 2 2 true dependency read after write 2 3 anti dependency write after read 2 4 output dependency write after write 3 implications 4 relevance in computing toggle relevance in computing subsection 4 1 processor design 4 2 compiler construction 5 see also 6 references toggle the table of contents data dependency 12 languages deutsch español فارسی magyar italiano 한국어 norsk bokmål русский српски srpski українська oʻzbekcha ўзбекча 中文 edit links article talk english read edit view history tools tools move to sidebar hide actions read edit view history general what links here related changes upload file permanent link page information cite this page get shortened url switch to legacy parser print export download as pdf printable version in other projects wikidata item appearance move to sidebar hide from wikipedia the free encyclopedia programming situation where an instruction refers to a prior instruction s data this article needs more citations please help improve this article by adding citations to reliable sources unsourced material may be challenged and removed find sources data dependency news newspapers books scholar jstor september 2024 learn how and when to remove this message a data dependency in computer science is a situation in which a program statement instruction refers to the data of a preceding statement in compiler theory the technique used to discover data dependencies among statements or instructions is called dependence analysis description edit assuming statement s 1 displaystyle s_ 1 and s 2 displaystyle s_ 2 s 2 displaystyle s_ 2 depends on s 1 displaystyle s_ 1 if i s 1 o s 2 o s 1 i s 2 o s 1 o s 2 displaystyle left i s_ 1 cap o s_ 2 right cup left o s_ 1 cap i s_ 2 right cup left o s_ 1 cap o s_ 2 right neq varnothing where i s i displaystyle i s_ i is the set of memory locations read by s i displaystyle s_ i o s j displaystyle o s_ j is the set of memory locations written by s j displaystyle s_ j and there is a feasible run time execution path from s 1 displaystyle s_ 1 to s 2 displaystyle s_ 2 these conditions are called bernstein s conditions named after arthur j bernstein 1 three cases exist anti dependence i s 1 o s 2 displaystyle i s_ 1 cap o s_ 2 neq varnothing s 1 s 2 displaystyle s_ 1 rightarrow s_ 2 and s 1 displaystyle s_ 1 reads something before s 2 displaystyle s_ 2 overwrites it flow data dependence o s 1 i s 2 displaystyle o s_ 1 cap i s_ 2 neq varnothing s 1 s 2 displaystyle s_ 1 rightarrow s_ 2 and s 1 displaystyle s_ 1 writes before something read by s 2 displaystyle s_ 2 output dependence o s 1 o s 2 displaystyle o s_ 1 cap o s_ 2 neq varnothing s 1 s 2 displaystyle s_ 1 rightarrow s_ 2 and both write the same memory location types edit data hazards edit data hazards occur when instructions that exhibit data dependence modify data in different stages of a pipeline ignoring potential data hazards can result in race conditions also termed race hazards there are three situations in which a data hazard can occur read after write raw a true dependency write after read war an anti dependency write after write waw an output dependency read after read rar a false dependency read after read rar is not a hazard case consider two instructions i1 and i2 with i1 occurring before i2 in program order read after write raw edit i2 tries to read a source before i1 writes to it a read after write raw data hazard refers to a situation where an instruction refers to a result that has not yet been calculated or retrieved this can occur because even though an instruction is executed after a prior instruction the prior instruction has been processed only partly through the pipeline example edit for example i1 r2 r5 r8 i2 r4 r2 r8 the first instruction is calculating a value to be saved in register r2 and the second is going to use this value to compute a result for register r4 however in a pipeline when operands are fetched for the 2nd operation the results from the first have not yet been saved and hence a data dependency occurs a data dependency occurs with instruction i2 as it is dependent on the completion of instruction i1 write after read war edit i2 tries to write a destination before it is read by i1 a write after read war data hazard represents a problem with concurrent execution example edit for example i1 r4 r1 r5 i2 r5 r1 r2 in any situation with a chance that i2 may finish before i1 i e with concurrent execution it must be ensured that the result of register r5 is not stored before i1 has had a chance to fetch the operands write after write waw edit i2 tries to write an operand before it is written by i1 a write after write waw data hazard may occur in a concurrent execution environment example edit for example i1 r5 r4 r7 i2 r5 r1 r3 the write back wb of i2 must be delayed until i1 finishes executing true dependency read after write edit a true dependency also known as a flow dependency or data dependency occurs when an instruction depends on the result of a previous instruction a violation of a true dependency leads to a read after write raw hazard 1 a 3 2 b a 3 c b instruction 3 is truly dependent on instruction 2 as the final value of c depends on the instruction updating b instruction 2 is truly dependent on instruction 1 as the final value of b depends on the instruction updating a since instruction 3 is truly dependent upon instruction 2 and instruction 2 is truly dependent on instruction 1 instruction 3 is also truly dependent on instruction 1 instruction level parallelism is therefore not an option in this example 2 anti dependency write after read edit an anti dependency occurs when an instruction requires a value that is later updated a violation of an anti dependency leads to a write after read war hazard in the following example instruction 2 anti depends on instruction 3 the ordering of these instructions cannot be changed nor can they be executed in parallel possibly changing the instruction ordering as this would affect the final value of a 1 b 3 2 a b 1 3 b 7 example mul r3 r1 r2 add r2 r5 r6 it is clear that there is anti dependence between these 2 instructions at first we read r2 then in second instruction we are writing a new value for it an anti dependency is an example of a name dependency that is renaming of variables could remove the dependency as in the next example 1 b 3 n b2 b 2 a b2 1 3 b 7 a new variable b2 has been declared as a copy of b in a new instruction instruction n the anti dependency between 2 and 3 has been removed meaning that these instructions may now be executed in parallel note that there is still a read after write dependency instruction 2 is truly dependent on instruction n which is truly dependent upon instruction 1 this dependency existed in the original version where instruction 2 was truly dependent on instruction 1 this dependency cannot be safely removed 2 output dependency write after write edit an output dependency occurs when the ordering of instructions will affect the final output value of a variable a violation of an output dependency leads to an write after write waw hazard in the example below there is an output dependency between instructions 3 and 1 changing the ordering of instructions in this example will change the final value of a thus these instructions cannot be executed in parallel 1 b 3 2 a b 1 3 b 7 as with anti dependencies output dependencies are name dependencies that is they may be removed through renaming of variables as in the below modification of the above example 1 b2 3 2 a b2 1 3 b 7 implications edit conventional programs are written assuming the sequential execution model under this model instructions execute one after the other atomically i e at any given point in time only one instruction is executed and in the order specified by the program however dependencies among statements or instructions may hinder parallelism parallel execution of multiple instructions either by a parallelizing compiler or by a processor exploiting instruction level parallelism recklessly executing multiple instructions without considering related dependences may cause danger of getting wrong results namely hazards relevance in computing edit data dependencies are relevant in various areas of computing particularly in processor design compiler construction parallel computing and concurrent programming processor design edit instruction pipelining in pipelined processors multiple instruction are executed in parallel in multiple pipeline stages thereby data dependencies between registers must be respected and handled in the processor pipeline most relevant are true dependencies that are resolved e g by stalling the pipeline or operand forwarding out of order execution modern processors often execute instructions out of their original order to improve performance thereby name dependencies between registers must be respected in addition to data dependencies and are resolved e g by register renaming or scoreboarding data dependencies are also relevant for memory accesses and must be respected by memory disambiguation techniques that execute memory access instructions loads and stores out of program order compiler construction edit data dependencies are relevant for various compiler optimizations e g instruction scheduling compilers must schedule instructions in a way that respects data dependencies this is crucial in optimizing compilers that rearrange code for better performance loop transformations in optimizing loops compilers need to consider data dependencies to apply transformations like loop unrolling fusion or tiling without changing the semantics of the program code motion when a compiler considers moving a piece of code it must ensure that data dependencies are not violated see also edit dependency analysis control dependency loop dependence analysis data dependence hazard computer architecture data hazards references edit bernstein arthur j 1 october 1966 analysis of programs for parallel processing ieee transactions on electronic computers ec 15 5 757 763 doi 10 1109 pgec 1966 264565 1 2 john l hennessy david a patterson 2003 computer architecture a quantitative approach 3rd ed morgan kaufmann isbn 1 55860 724 2 cite book cs1 maint multiple names authors list link retrieved from https en wikipedia org w index php title data_dependency oldid 1310777676 categories compilers analysis of parallel algorithms hidden categories articles with short description short description with empty wikidata description articles needing additional references from september 2024 all articles needing additional references cs1 long volume value cs1 maint multiple names authors list this page was last edited on 11 september 2025 at 15 27 utc page was rendered with parsoid text is available under the creative commons attribution sharealike 4 0 license additional terms may apply by using this site you agree to the terms of use and privacy policy wikipedia is a registered trademark of the wikimedia foundation inc a non profit organization privacy policy about wikipedia disclaimers contact wikipedia legal safety contacts code of conduct developers statistics cookie statement mobile view search search toggle the table of contents data dependency 12 languages add topic