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distributed shared memory wikipedia jump to content main menu main menu move to sidebar hide navigation main page contents current events random article about wikipedia contact us contribute help learn to edit community portal recent changes upload file special pages search search appearance donate create account log in personal tools donate create account log in contents move to sidebar hide top 1 overview toggle overview subsection 1 1 comparison with message passing 2 directory memory coherence toggle directory memory coherence subsection 2 1 states 2 2 home centric request and response 2 3 requester centric request and response 3 consistency models 4 replication 5 release and entry consistency toggle release and entry consistency subsection 5 1 examples 6 see also 7 references 8 external links toggle the table of contents distributed shared memory 9 languages العربية български deutsch español فارسی 日本語 한국어 српски srpski 中文 edit links article talk english read edit view history tools tools move to sidebar hide actions read edit view history general what links here related changes upload file permanent link page information cite this page get shortened url switch to legacy parser print export download as pdf printable version in other projects wikidata item appearance move to sidebar hide from wikipedia the free encyclopedia computer memory architecture dgas redirects here for the dga awards see directors guild of america award this article has multiple issues please help improve it or discuss these issues on the talk page learn how and when to remove these messages this article is written like a textbook please help rewrite it in a neutral encyclopedic style january 2026 this article needs more citations please help improve this article by adding citations to reliable sources unsourced material may be challenged and removed find sources distributed shared memory news newspapers books scholar jstor january 2022 learn how and when to remove this message learn how and when to remove this message distributed shared memory implementation in computer science distributed shared memory dsm is a form of memory architecture where physically separated memories can be addressed as a single shared address space the term shared does not mean that there is a single centralized memory but that the address space is shared i e the same physical address on two processors refers to the same location in memory 1 201 distributed global address space dgas is a similar term for a wide class of software and hardware implementations in which each node of a cluster has access to shared memory in addition to each node s private i e not shared memory overview edit dsm can be achieved via software as well as hardware hardware examples include cache coherence circuits and network interface controllers there are three ways of implementing dsm page based approach using virtual memory shared variable approach using routines to access shared variables and object based approach ideally accessing shared data through object oriented discipline dsm scales well with a large number of nodes and its message passing is hidden it can handle complex and large databases without replication or sending the data to processes and is generally cheaper than using a multiprocessor system it provides large virtual memory space programs are more portable due to common programming interfaces and shield programmers from sending or receiving primitives 2 it is generally slower to access than non distributed shared memory and must provide additional protection against simultaneous accesses to shared data dsm may incur a performance penalty there is little programmer control over actual messages being generated and consistency models are needed to write correct programs comparison with message passing edit message passing distributed shared memory variables have to be marshalled variables are shared directly cost of communication is obvious cost of communication is invisible processes are protected by having private address space processes could cause error by altering data processes should execute at the same time executing the processes may happen with non overlapping lifetimes software dsm systems also have the flexibility to organize the shared memory region in different ways the page based approach organizes shared memory into pages of fixed size in contrast the object based approach organizes the shared memory region as an abstract space for storing shareable objects of variable sizes another commonly seen implementation uses a tuple space in which the unit of sharing is a tuple shared memory architecture may involve separating memory into shared parts distributed amongst nodes and main memory or distributing all memory between nodes a coherence protocol chosen in accordance with a consistency model maintains memory coherence directory memory coherence edit main article directory based cache coherence memory coherence is necessary such that the system which organizes the dsm is able to track and maintain the state of data blocks in nodes across the memories comprising the system a directory is one such mechanism which maintains the state of cache blocks moving around the system states edit a state diagram of a block of memory in a dsm a block is owned if one of the nodes has the block in state em a basic dsm will track at least three states among nodes for any given block in the directory 3 there will be some state to dictate the block as uncached u a state to dictate a block as exclusively owned or modified owned em and a state to dictate a block as shared s as blocks come into the directory organization they will transition from u to em ownership state in the initial node the state can transition to s when other nodes begin reading the block there are two primary methods for allowing the system to track where blocks are cached and in what condition across each node home centric request response uses the home to service requests and drive states whereas requester centric allows each node to drive and manage its own requests through the home home centric request and response edit in a home centric system the dsm will avoid having to handle request response races between nodes by allowing only one transaction to occur at a time until the home node has decided that the transaction is finished usually when the home has received every responding processor s response to the request an example of this is intel s qpi home source mode 4 the advantages of this approach are that it is simple to implement but its request response strategy is slow and buffered due to the home node s limitations requester centric request and response edit sequential invocations and responses in dsm in a requester centric system the dsm will allow nodes to talk at will to each other through the home this means that multiple nodes can attempt to start a transaction but this requires additional considerations to ensure coherence for example when one node is processing a block if it receives a request for that block from another node it will send a nack negative acknowledgement to tell the initiator that the processing node cannot fulfill that request right away an example of this is intel s qpi snoop source mode 4 this approach is fast but it does not naturally prevent race conditions and generates more bus traffic consistency models edit the dsm must follow certain rules to maintain consistency over how read and write order is viewed among nodes called the system s consistency model in a situation where there are n processes and mi memory operations for each process i and that all the operations are executed sequentially m1 m2 mn m1 m2 mn are possible interleavings of the operations the issue with this conclusion is determining the correctness of the interleaved operations memory coherence for dsm defines which interleavings are permitted replication edit there are two types of replication algorithms read replication and write replication in read replication multiple nodes can read at the same time but only one node can write while in write replication multiple nodes can read and write at the same time the write requests are handled by a sequencer replication of shared data in general tends to reduce network traffic promote increased parallelism and result in fewer page faults preserving coherence and consistency may become more challenging release and entry consistency edit release consistency is when a process exits a critical section new values of the variables are propagated to all sites entry consistency is when a process enters a critical section it will automatically update the values of the shared variables view based consistency is a variant of entry consistency except the shared variables of a critical section are automatically detected by the system examples edit kerrighed open ssi mosix treadmarks vodca archived 2016 02 15 at the wayback machine dipc see also edit distributed cache type of computer cache memory virtualization computer science term single system image cluster dedicated operating system pages displaying short descriptions of redirect targets remote direct memory access low level hardware direct memory access references edit patterson david a hennessy john l 2006 computer architecture a quantitative approach 4th ed burlington massachusetts morgan kaufmann isbn 978 01 2370490 0 client challenge www scribd com retrieved 2026 10 02 solihin yan 2015 fundamentals of parallel multicore architecture boca raton florida chapman and hall crc pp 339 340 isbn 9781482211184 1 2 sorin daniel j hill mark d wood david a 2011 a primer on memory consistency and cache coherence morgan claypool p 174 isbn 978 16 0845564 5 external links edit distributed shared cache memory coherence in shared virtual memory systems by kai li paul hudak published in acm transactions on computer systems volume 7 issue 4 nov 1989 v t e parallel computing general distributed computing parallel computing parallel algorithm massively parallel cloud computing high performance computing multiprocessing manycore processor gpgpu computer network systolic array levels bit instruction thread task data memory loop pipeline multithreading temporal simultaneous smt simultaneous and heterogenous speculative spmt preemptive cooperative clustered multi thread cmt hardware scout theory pram model pem model analysis of parallel algorithms amdahl s law gustafson s law cost efficiency karp flatt metric slowdown speedup elements process thread fiber instruction window array coordination multiprocessing memory coherence cache coherence cache invalidation barrier synchronization application checkpointing programming stream processing dataflow programming models implicit parallelism explicit parallelism concurrency non blocking algorithm hardware flynn s taxonomy sisd simd array processing simt pipelined processing associative processing misd mimd dataflow architecture pipelined processor superscalar processor vector processor multiprocessor symmetric asymmetric memory shared distributed distributed shared uma numa coma massively parallel computer computer cluster beowulf cluster grid computer hardware acceleration apis ateji px boost chapel hpx charm cilk coarray fortran cuda dryad c amp global arrays gpuopen mpi openmp opencl openhmpp openacc parallel extensions pvm pthreads raftlib rocm upc tbb zpl problems automatic parallelization cache stampede deadlock deterministic algorithm embarrassingly parallel parallel slowdown race condition software lockout scalability starvation category parallel computing retrieved from https en wikipedia org w index php title distributed_shared_memory oldid 1378028712 category distributed computing architecture hidden categories articles with short description short description is different from wikidata wikipedia articles with style issues from january 2026 all articles with style issues articles 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