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table version in other projects wikidata item appearance move to sidebar hide from wikipedia the free encyclopedia computer machine code instruction in computer engineering halt and catch fire known by the assembly language mnemonic hcf is an idiom referring to a computer machine code instruction that causes the computer s central processing unit cpu to cease meaningful operation typically requiring a restart of the computer it originally referred to a fictitious instruction in ibm system 360 computers introduced in 1964 making a joke about its numerous non obvious instruction mnemonics after the introduction of the mc6800 processor in 1974 a design flaw was discovered by programmers due to incomplete opcode decoding two illegal opcodes 0x9d and 0xdd will cause the program counter on the processor to increment endlessly which locks the processor until reset those codes have been unofficially named hcf during the design process of the mc6802 engineers originally planned to remove this instruction but kept it as is for testing purposes as a result hcf was officially recognized as a real instruction 1 2 later hcf became a humorous catch all term for instructions that may freeze a processor including intentional instructions for testing purposes and unintentional illegal instructions some are considered hardware defects and if the system is shared a malicious user can execute them to launch a denial of service attack in the case of real instructions the implication of this expression is that whereas in most cases in which a cpu executes an unintended instruction a bug in the code the computer may still be able to recover in the case of an hcf instruction there is by definition no way for the system to recover without a restart the expression catch fire facetiously suggests that the unusual state the computer hardware is placed in may cause permanent physical damage 3 origins edit the z1 1938 and z3 1941 computers built by konrad zuse contained illegal sequences of instructions which damaged the hardware if executed by accident 4 apocryphal stories connect this term with an illegal opcode in ibm system 360 a processor upon encountering the instruction would repeatedly access one specific location in the magnetic core memory causing it become very hot and possibly catch fire 5 6 in a computer s assembly language mnemonics are used that are directly equivalent to machine code instructions the mnemonics are frequently three letters long such as add cmp to compare two numbers and jmp jump to a different location in the program the hcf instruction was originally a fictitious assembly language instruction said to be under development at ibm for use in their system 360 computers along with many other amusing three letter acronyms like xpr execute programmer and cai corrupt accounting information and similar to other joke mnemonics such as sdi for self destruct immediately 7 and crn for convert to roman numerals 8 a list of such mnemonics including hcf shows up as overextended mnemonics in the april 1980 creative computing flip side parody issue 9 in modern cpus edit cpu designers sometimes incorporate one or more undocumented machine code instructions for testing purposes such as the ibm system 360 diagnose instruction 10 motorola 6800 edit the motorola 6800 microprocessor was the first for which an undocumented assembly mnemonic hcf became widely known the operation codes opcodes the portions of the machine language instructions that specify an operation to be performed hexadecimal 9d and dd were reported and given the unofficial mnemonic hcf in a december 1977 article by gerry wheeler in byte magazine on undocumented opcodes 11 wheeler noted that motorola reported 197 valid operation codes for the m6800 processor and so inferred that with 256 possible 8 bit combinations there must be 59 invalid instructions he described the hcf as a big surprise and said of the catch fire portion of the moniker well almost when this instruction is run the only way to see what it is doing is with an oscilloscope from the user s point of view the machine halts and defies most attempts to get it restarted those persons with indicator lamps on the address bus will see that the processor begins to read all of the memory sequentially very quickly in effect the address bus turns into a 16 bit counter however the processor takes no notice of what it is reading it just reads 11 another author wrote in 2002 in the old days of the motorola 6800 microprocessor instruction code dd caused the processor to go into an endless loop reading from each memory address in order other engineers referred to this as the halt and catch fire hcf instruction but we remembered the code by calling it the drop dead instruction drop dead mode was wonderful for spotting hardware timing and address logic problems with a scope all of the address and clock lines were nice cycling square waves 12 the 6800 s behavior when encountering hcf was known to motorola by 1976 when the 6800 encounters the hcf instruction the processor never finds the end of it endlessly incrementing its program counter until the cpu is reset 13 hence the address bus effectively becomes a counter allowing the operation of all address lines to be quickly verified once the processor entered this mode it is not responsive to interrupts so normal operation can only be restored by a reset hence the drop dead and halt and catch fire monikers these references are thus to the unresponsive behavior of the cpu in this state and not to any form of erratic behavior citation needed motorola kept the hcf behavior in the 6802 variant of the processor which released in 1977 as an intentional self test for the 6802 s 128 bytes of onboard ram other hcf like instructions were found later on the motorola 6800 when executing undocumented opcodes fd cycling at half the rate of 9d dd or cd ed cycling at a human readable very low frequency on a limited number of high address lines 14 hcf is believed to be the first built in self test feature on a motorola microprocessor 2 intel x86 edit see also hlt x86 instruction and pentium f00f bug the intel 8086 and all subsequent x86 processors have an hlt halt instruction opcode f4 which stops instruction execution and places the processor in a halt state an enabled interrupt a debug exception the binit signal the init signal or the reset signal resumes execution which means the processor can always be restarted 15 some of the early intel dx4 chips have a problem with the hlt instruction and cannot be restarted after this instruction is used which disables the computer and turns hlt into more of an hcf instruction the linux kernel has a no hlt option telling linux to run an infinite loop instead of using hlt which allows users of these broken chips to use linux 16 the 80286 has the undocumented opcode 0f 04 causing the cpu to hang when executed the only way out is a cpu reset citation needed 17 in some implementations the opcode is emulated through bios as a halting sequence 18 many computers in the intel pentium line can be locked up by executing an invalid instruction f00f c7c8 which causes the computer to lock up this became known as the pentium f00f bug no functional quality compiler creates the instruction but a malicious programmer can insert it into code to render an afflicted computer inoperable until the machine is power cycled since its discovery workarounds have been developed to prevent it from locking the computer and the bug has been eliminated in subsequent intel processors 19 20 during black hat usa 2017 christopher domas showed that he found a new halt and catch fire instruction 21 22 on an undisclosed x86 processor model using his own x86 processor fuzzer called sandsifter 23 other cpus edit the nmos mos technology 6502 has 12 invalid instructions which cause the program counter to fail to fetch the next instruction locking up the cpu and requiring a processor reset 24 25 the wdc version of the cmos 65c02 as well as the 65c816 has the stp stop opcode db instruction when executed stp will stop the processor s internal clock causing all processing to cease also the processor will be unresponsive to all inputs except resb reset the only way to clear the effects of an stp instruction is to toggle resb on the zilog z80 executing di disable interrupts followed by halt wait for an interrupt results in the cpu staying frozen indefinitely waiting for an interrupt that cannot happen however the non maskable interrupt signal can be used to break out of this state making this pair not a true hcf 26 27 the nmi signal is on pin 17 of the original 40 pin dip package 28 29 the pair will only result in a hcf condition if either the nmi pin is connected directly to the 5v rail making the generation of that signal impossible or if the interrupt routine that services nmi ends with a return placing it back in the halt state the sm83 processor a 30 core in the game boy s lr35902 system on chip has a similar issue triggered by two consecutive halts with interrupts disabled b 31 the core itself contains 11 opcodes that fully lock the cpu when executed 32 the sc61860 mainly used in sharp pocket computers in the 1980s and 1990s has an undocumented hcf instruction with the opcode 7b 33 see also edit cyrix coma bug pentium f00f bug killer poke magic smoke lp0 on fire write only memory joke nop code notes edit the sm83 cpu is similar to the z80 but not directly related when interrupts are disabled the halt instruction on the game boy cpu does not pause the cpu but rather prevents the cpu s program counter from incrementing on the instruction immediately following the halt effectively doubling the instruction after the halt or for a multi byte instruction doubling the first byte and separating off the original last byte into a new single byte instruction if the instruction after the halt is itself a halt then as halt is a single byte instruction the cpu effectively sees an infinite series of halts causing the system to lock up references edit 6800 instruction set pdf bryan s old computers archived pdf from the original on 2021 05 01 retrieved 2022 04 09 1 2 daniels r gary bruce william april 1985 built in self test trends in motorola microprocessors ieee design test 2 2 64 71 bibcode 1985idtc 2 64d doi 10 1109 mdt 1985 294865 s2cid 22719798 to add insult to injury we discovered that we had an illegal hacof an instruction that our customers found on the mc6800 it was an unused opcode an illegal instruction when executed inadvertently the program counter would increment indefinitely the problem which was caused by incomplete opcode decoding was a nuisance because reset was the only means of terminating the instruction during the design process we figured out how to eliminate the hacof instruction about that time the product engineers came to us with an idea they said you know what we d really like some way to quickly test the ram if we could somehow point the program counter at the first ram address and then just increment through the ram we could test it a lot faster since the hacof instruction did precisely that and we really didn t want to invest the effort needed to remove it we replied have we got a deal for you hacof thus became the first intentional built in self test feature on a motorola microprocessor jargon file entry for the hcf assembly mnemonic archived from the original on 2012 05 20 retrieved 2014 05 04 rojas raúl april june 1997 konrad zuse s legacy the architecture of the z1 and z3 pdf ieee annals of the history of computing 19 2 5 16 9 10 doi 10 1109 85 586067 archived pdf from the original on 2022 07 03 retrieved 2022 07 03 p 10 there are a lot of details that the engineer designing the microprogram must keep in mind otherwise short circuits can destroy the hardware the z1 with its mechanical design was still more sensitive in this respect than the z3 even after it was completed there were sequences of instructions that the programmer had to avoid in order not to damage the hardware one of those sequences was inadvertently tried at the berlin museum of technology and transportation which led to slight damaging of the reconstructed z1 in 1994 12 pages clements alan 2006 10 28 embedding ethics in computer architecture asee ieee frontiers in education conference 36 ed p 4 archived from the original on 2022 04 30 retrieved 2018 03 02 kohler eddie 2005 04 04 cs111 lecture 1 pdf p 2 archived pdf from the original on 2018 03 02 retrieved 2018 03 02 dunlap bryan a proposed instruction set physics department the ohio state university archived from the original on 2017 09 08 retrieved 2016 06 20 cirsovius werner far out op codes archived from the original on 2016 03 05 retrieved 2015 05 28 overextended mnemonics creative computing 6 4 17 hex flip side april 1980 retrieved 2017 03 12 ibm system 360 principles of operation pdf ibm archived pdf from the original on 2012 02 29 retrieved 2014 07 02 1 2 wheeler gerry december 1977 undocumented m6800 instructions byte vol 2 no 12 pp 46 47 retrieved 2023 11 20 the mnemonics are of course assigned by me agans david j 2002 debugging the 9 indispensable rules for finding even the most elusive software and hardware problems new york usa american management association p 77 isbn 978 0 81442678 4 oclc 52043345 archived from the original on 2014 07 26 retrieved 2016 10 30 daniels r gary bruce william april 1985 built in self test trends in motorola microprocessors ieee design test of computers 2 2 64 bibcode 1985idtc 2 64d doi 10 1109 mdt 1985 294865 s2cid 22719798 demeulemeester samuel 2019 07 17 investigating the hcf halt catch fire instruction on motorola 6800 x86 fr doc tb s r d lab archived from the original on 2022 03 31 retrieved 2022 04 09 x86 instruction set reference hlt archived from the original on 2014 07 14 retrieved 2014 07 02 gortmaker paul 2003 03 21 the linux boot prompt how to pdf the linux documentation project archived pdf from the original on 2015 07 06 retrieved 2014 07 02 re undocumented opcodes hint_nop archived from the original on 2004 11 06 retrieved 2010 11 07 re also some undocumented 0fh opcodes archived from the original on 2003 06 26 retrieved 2010 11 07 collins robert r 1998 05 01 the pentium f00f bug workarounds for a nasty problem dr dobb s journal archived from the original on 2022 04 30 retrieved 2014 08 12 pentium processor specification update pdf intel corporation january 1999 pp 51 52 order number 242480 041 archived pdf from the original on 2016 03 04 retrieved 2006 11 02 breaking the x86 isa pdf pdf christopher domas archived pdf from the original on 2018 01 04 retrieved 2017 12 09 breaking the x86 isa video christopher domas 2017 08 31 archived from the original on 2021 12 21 retrieved 2017 12 09 sandsifter the x86 processor fuzzer christopher domas archived from the original on 2017 10 25 retrieved 2017 12 09 steil michael how mos 6502 illegal opcodes really work pagetable com archived from the original on 2...