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mmu 68881 68 ec 030 132 pin qfp 128 pin pga 25 40 10 11 32 68881 1991 68040 179 pin pga 12 184 pin qfp 13 20 40 32 mmu fpu 68 lc 040 179 pin pga 12 184 pin qfp 13 20 33 32 mmu 68 ec 040 179 pin pga 12 184 pin qfp 12 20 33 13 32 1994 68060 206 pin pga 14 15 50 133 16 17 32 mmu fpu 68 lc 060 206 pin pga 14 15 208 pin qfp 50 133 16 17 32 mmu 68 ec 060 206 pin pga 14 15 50 133 16 17 32 uses edit the genesis has a 68000 clocked at 7 6 mhz as its main cpu the 680x0 line of processors has been used in a variety of systems from high end texas instruments calculators the ti 89 ti 92 and voyage 200 lines to all of the members of the palm pilot series that run palm os 1 x to 4 x os 5 x is arm based and even radiation hardened versions in the critical control systems of the space shuttle the 680x0 family was well known for powering desktop computers and video game consoles such as the macintosh 128k amiga sinclair ql atari st genesis mega drive neo geo aes neo geo cd cdtv they were the processors of choice in the 1980s for unix workstations and servers such as at t s unix pc tandy s model 16 16b 6000 sun microsystems sun 1 sun 2 sun 3 next computer silicon graphics sgi and numerous others the saturn uses the 68000 for audio processing and other i o tasks while the jaguar includes a 68000 intended for basic system control and input processing but was frequently used for running game logic many arcade boards also use processors from the 680x0 family including those from sega capcom and snk the first several versions of adobe s postscript interpreters were 68000 based the 68000 in the apple laserwriter and laserwriter plus was clocked faster than the version used then in macintosh computers a fast 68030 in later postscript interpreters including the standard resolution laserwriter iintx iif and iig also 300 dpi the higher resolution laserwriter pro 600 series usually 600 dpi but limited to 300 dpi with minimum ram installed and the very high resolution linotronic imagesetters the 200ps 1500 dpi and 300ps 2500 dpi thereafter adobe generally preferred a risc for its processor as its competitors with their postscript clones had already gone with riscs often an amd 29000 series the early 68000 based adobe postscript interpreters and their hardware were named for cold war era u s rockets and missiles atlas redstone etc microcontrollers derived from the 680x0 family have been used in a huge variety of applications cpu32 and coldfire microcontrollers have been manufactured in the millions as automotive engine controllers many proprietary video editing systems also use processors from the 680x0 family including the macrosystem casablanca 1997 which was a black box with an easy to use graphic interface intended for the amateur and hobby videographer market it is also worth noting its earlier bigger and more professional counterpart the draco 1995 the groundbreaking quantel paintbox series of early based 24 bit paint and effects system was originally released in 1981 and during its lifetime used nearly the entire range of processors from the 680x0 family except the 68060 which was never implemented in its design another contender in the video arena the abekas 8150 dve system used the 68ec030 and the play trinity later renamed globecaster uses several 68030s the bosch fgs 4000 4500 video graphics system manufactured by robert bosch corporation later bts 1983 used a 68000 as its main processor it drove several others to perform 3d animation in a computer that could easily apply gouraud and phong shading and ran a modified version of the motorola versados operating system architecture edit motorola 68000 series registers 3 1 2 3 1 5 0 7 0 0 bit position data registers d0 data 0 d1 data 1 d2 data 2 d3 data 3 d4 data 4 d5 data 5 d6 data 6 d7 data 7 address registers a0 address 0 a1 address 1 a2 address 2 a3 address 3 a4 address 4 a5 address 5 a6 address 6 stack pointers a7 usp stack pointer user a7 ssp stack pointer supervisor program counter pc program counter status register 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 bit position t s m 0 i 0 0 0 x n z v c sr people who are familiar with the pdp 11 or vax usually feel comfortable with the 68000 series with the exception of the split of general purpose registers into specialized data and address registers the 68000 architecture is in many ways a 32 bit pdp 11 it had a more orthogonal instruction set than those of many processors that came before e g 8080 and after e g x86 that is it was typically possible to combine operations freely with operands rather than being restricted to using certain addressing modes with certain instructions this property made programming relatively easy for humans and also made it easier to write code generators for compilers the 68000 series has eight 32 bit general purpose data registers d0 d7 and eight address registers a0 a7 the last address register is the stack pointer and assemblers accept the label sp as equivalent to a7 in addition it has a 16 bit status register the upper 8 bits is the system byte and modification of it is privileged the lower 8 bits is the user byte also known as the condition code register ccr and modification of it is not privileged the 68000 comparison arithmetic and logic operations modify condition codes to record their results for use by later conditional jumps the condition code bits are zero z carry c overflow v extend x and negative n the extend x flag deserves special mention because it is separate from the carry flag this permits the extra bit from arithmetic logic and shift operations to be separated from the carry for flow of control and linkage while the 68000 had a supervisor mode it did not meet the popek and goldberg virtualization requirements due to the single instruction move from sr which copies the status register to another register being unprivileged but sensitive in the motorola 68010 and later this was made privileged to better support virtualization software the 68000 series instruction set can be divided into the following broad categories load and store move arithmetic add sub muls mulu divs divu bit shifting asl asr lsl lsr bit rotation ror rol roxl roxr logic operations and or not eor type conversion byte to word and vice versa conditional and unconditional branches bra bcc beq bne bhi blo bmi bpl etc subroutine invocation and return bsr rts stack management link unlk pea causing and responding to interrupts exception handling there is no equivalent to the x86 cpuid instruction to determine what cpu or mmu or fpu is present the motorola 68020 added some new instructions that include some minor improvements and extensions to the supervisor state several instructions for software management of a multiprocessing system which were removed in the 68060 some support for high level languages which did not get used much and was removed from future 680x0 processors bigger multiply 32 32 64 bits and divide 64 32 32 bits quotient and 32 bits remainder instructions and bit field manipulations the standard addressing modes are register direct data register e g d0 address register e g a0 register indirect simple address e g a0 address with post increment e g a0 address with pre decrement e g a0 address with a 16 bit signed offset e g 16 a0 register indirect with index register and 8 bit signed offset e g 8 a0 d0 or 8 a0 a1 for a0 and a0 the actual increment or decrement value is dependent on the operand size a byte access adjusts the address register by 1 a word by 2 and a long by 4 pc program counter relative with displacement relative 16 bit signed offset e g 16 pc this mode was very useful for position independent code relative with 8 bit signed offset with index e g 8 pc d2 absolute memory location either a number e g 4000 or a symbolic name translated by the assembler most assemblers used the symbol for hexadecimal instead of 0x or a trailing h there were 16 and 32 bit versions of this addressing mode immediate mode data stored in the instruction e g 400 quick immediate mode 3 bit unsigned or 8 bit signed with moveq with value stored in opcode in addq and subq 0 is the equivalent to 8 e g moveq 0 d0 was quicker than clr l d0 though both made d0 equal to 0 plus access to the status register and in later models other special registers the motorola 68020 added a scaled indexing address mode and added another level of indirection to many of the pre existing modes most instructions have dot letter suffixes permitting operations to occur on 8 bit bytes b 16 bit words w and 32 bit longs l most instructions are dyadic that is the operation has a source and a destination and the destination is changed notable instructions were arithmetic add sub mulu unsigned multiply muls signed multiply divu divs neg additive negation and cmp a comparison done by subtracting the arguments without storing the result setting the status bits binary coded decimal arithmetic abcd nbcd and sbcd logic eor exclusive or and not logical not or inclusive or shifting logical i e right shifts put zero in the most significant bit lsl lsr arithmetic shifts i e sign extend the most significant bit asr asl rotates through extend and not roxl roxr rol ror bit test and manipulation in memory or data register bset set to 1 bclr clear to 0 bchg invert and btst no change all of these instructions first test the destination bit and set clear the ccr z bit if the destination bit is 0 1 respectively multiprocessing control tas test and set performed an indivisible bus operation permitting semaphores to be used to synchronize several processors sharing a single memory flow of control jmp jump jsr jump to subroutine bsr relative address jump to subroutine rts return from subroutine rte return from exception i e an interrupt trap trigger a software exception similar to software interrupt chk a conditional software exception branch bcc where the cc specified one of 14 tests of the condition codes in the status register equal greater than less than carry and most combinations and logical inversions available from the status register of the remaining two possible conditions always true and always false bra branch always has a separate mnemonic and bsr branch to subroutine takes the encoding that would otherwise have been branch never decrement and branch dbcc where cc was as for the branch instructions which provided the condition was false decremented the low word of a d register and if the result was not 1 ffff branched to a destination this use of 1 instead of 0 as the terminating value allowed the easy coding of loops that had to do nothing if the count was 0 to start with with no need for another check before entering the loop this also facilitated nesting of dbcc last generation edit the 4th generation 68060 provided equivalent functionality though not instruction set architecture compatibility to most of the features of the intel p5 microarchitecture other 680x0 cpus edit motorola mainly used even numbers for major revisions to the cpu core such as 68000 68020 68040 and 68060 the 68010 was a revised version of the 68000 with minor modifications to the core and likewise the 68030 was a revised 68020 with some more powerful features none of them significant enough to classify as a major upgrade to the core the 68050 was reportedly a minor upgrade of the 68040 that lost a battle for resources within motorola competing against projects that had been scheduled to succeed it the 0 5μm low power low cost lp040 and the superscalar superpipelined q borrowing from the 88110 and anticipated as the 68060 18 subsequent reports indicated that motorola had considered the 68050 as not meriting the necessary investment in production of the part 19 odd numbered releases had always been reactions to issues raised within the prior even numbered part hence it was generally expected that the 68050 would have reduced the 68040 s power consumption and thus heat dissipation improved exception handling in the fpu used a smaller feature size and optimized the microcode in line with program use of instructions many of these optimizations were included with the 68060 and were part of its design goals for any number of reasons likely that the 68060 was in development that the 80486 was not progressing as quickly as motorola assumed it would and that the 68060 was a demanding project the 68050 was cancelled early in development there was no official revision of the 68060 as motorola was in the process of shifting away from the 68000 and 88000 processor lines into its new powerpc business so the 68070 was never developed had it been produced it would have been a revised 68060 likely with a superior fpu pipelining was widely speculated upon on usenet groups there was a cpu with the 68070 designation however this was not officially part of motorola s 680x0 lineup and was instead produced by philips it was also produced many years prior to the release of the 68060 as well as its predecessors this 68070 was a licensed and somewhat slower version of the 16 32 bit 68000 with a basic dma controller i 2 c host and an on chip serial port and was used as the main cpu in the philips cd i motorola had announced a product roadmap beyond the 68060 which includes the 68080 rated at 200 350 mips due by 1995 and a product rated at 800 mips possibly with the name 68100 by 2000 19 all of these plans fell through after motorola stopped development of the 680x0 series in 1994 shortly after the release of the 68060 the last cpu in the 680x0 series in favor of powerpc a cpu with the 68080 designation was also produced however much like with the 68070 above this was also not officially part of the 680x0 series and was produced as a modern fpga implementation of the 680x0 series with various improvements 1 other variants edit the personal computers xt 370 and at 370 pc based ibm compatible mainframes each included two modified motorola 68000 processors with custom microcode to emulate s 370 mainframe instructions 20 21 an arizona based company edge computer corp reportedly founded by former honeywell designers produced processors compatible with the 68000 series these being claimed as having a three to five times performance and 18 to 24 months time advantage over motorola s own products 22 in 1987 the company introduced the edge 1000 range of 32 bit superminicomputers implementing the motorola instruction set in the edge mainframe architecture employing two independent pipelines an instruction fetch pipeline ifp and operand executive pipeline oep relying on a branch prediction unit featuring a 4096 entry branch cache retrieving instructions and operands over multiple buses 23 an agreement between edge computer and olivetti subsequently led to the latter introducing products in its own linea duo range based on edge computer s machines 24 the company was subsequently renamed to edgcore technology inc 25 12 also reported as edgecore technology inc 26 edgcore s deal with olivetti in 1987 to supply ...