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the (434), and (119), #instruction (67), pdp (52), register (48), for (47), address (44), instructions (43), bit (41), #processor (41), set (40), dest (40), edit (39), stack (39), memory (38), operand (38), reg (36), are (35), with (32), word (32), from (31), branch (30), that (27), addressing (27), opcode (27), code (26), src (26), floating (25), operation (24), bus (23), can (23), character (22), used (22), data (22), bits (22), modes (22), point (21), string (21), registers (21), not (20), then (20), two (19), condition (19), move (19), one (18), byte (18), this (17), program (17), its (17), which (17), next (17), space (17), mode (16), words (16), device (15), trap (15), psw (15), use (14), but (14), routine (14), return (14), deferred (14), mnemonic (14), digital (13), dec (13), pointer (13), location (13), pdf (12), pdp11 (12), example (12), value (12), add (11), table (11), also (11), grant (11), any (11), general (11), single (11), subroutine (11), bytes (11), shift (11), codes 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Text of the page (random words):
s low order byte or by a memory location words are specified by a register number or by the memory location of the low order byte which must be an even location in most instructions that take operands bit 15 is set to specify byte addressing or clear to specify word addressing in the lists in the following two sections the assembly language programmer appended b to the instruction symbol to specify a byte operation for example mov became movb a few instructions for example mark and sob were not implemented on some pdp 11 models double operand instructions edit the high order four bits specify the operation to be performed with bit 15 generally selecting word versus byte addressing two groups of six bits specify the source operand addressing mode and the destination operand addressing mode as defined above this group of instructions takes up 75 of available opcodes 15 12 11 9 8 6 5 3 2 0 opcode src register dest register opcode mnemonic operation 01 mov move dest src movb to register sign extends to bits 8 15 11 movb 02 cmp compare src dest 12 cmpb 03 bit bit test src dest 13 bitb 04 bic bit clear dest dest 1 src 14 bicb 05 bis bit set dest dest src 15 bisb 06 add add dest dest src 16 sub subtract dest dest src the add and sub instructions use word addressing and have no byte oriented variations due to encoding limitations some two operand instructions utilize an addressing mode operand and a register operand 15 9 8 6 5 3 2 0 opcode reg src dest register where a register pair is used written below as reg reg 1 the first register contains the high order portion of the operand and must be an even numbered register the next higher numbered register contains the low order portion of the operand or the remainder an exception is the multiply instruction reg may be odd but if it is the high 16 bits of the result are not stored opcode mnemonic operation 070 mul signed multiply reg reg 1 reg src 071 div signed divide compute reg reg 1 src reg quotient reg 1 remainder 072 ash arithmetic shift if src 5 0 0 then reg shift right reg src 5 0 else reg shift left reg src 5 0 073 ashc arithmetic shift combined 32 bit if src 5 0 0 then reg reg 1 shift right reg reg 1 src 5 0 else reg reg 1 shift left reg reg 1 src 5 0 074 xor exclusive or dest dest reg single operand instructions edit the high order ten bits specify the operation to be performed with bit 15 generally selecting byte versus word addressing a single group of six bits specifies the operand as defined above 15 6 5 3 2 0 opcode src dest register opcode mnemonic operation 0001 jmp jump pc ea src 0003 swab swap bytes of word dest 0 7 dest 8 15 0050 clr clear dest 0 1050 clrb 0051 com complement dest 1 dest 1051 comb 0052 inc increment dest dest 1 1052 incb 0053 dec decrement dest dest 1 1053 decb 0054 neg negate dest 0 dest 1054 negb 0055 adc add carry dest dest c flag 1055 adcb 0056 sbc subtract carry dest dest c flag 1056 sbcb 0057 tst test src src 1057 tstb 0060 ror rotate right c s 0 s 0 14 s 1 15 s 15 c 1060 rorb rotate right byte c s 0 s 0 6 s 1 7 s 7 c 0061 rol rotate left c s 15 s 1 15 s 0 14 s 0 c 1061 rolb rotate left byte c s 7 s 1 7 s 0 6 s 0 c 0062 asr arithmetic shift right dest dest 2 1062 asrb 0063 asl arithmetic shift left dest dest x 2 1063 aslb 1064 mtps move to psw psw src 0065 mfpi move from previous i space sp src 1065 mfpd move from previous d space sp src 0066 mtpi move to previous i space dest sp 1066 mtpd move to previous d space dest sp 0067 sxt sign extend if n flag 0 then dest 0 else dest 1 1067 mfps move from psw dest psw branch instructions edit in most branch instructions whether the branch is taken is based on the state of the condition codes a branch instruction is typically preceded by a two operand cmp compare or bit bit test or a one operand tst test instruction arithmetic and logic instructions also set the condition codes in contrast to intel processors in the x86 architecture mov instructions set them too so a branch instruction could be used to branch depending on whether the value moved was zero or negative the high order byte of the instruction specifies the operation bits 9 through 15 are the op code and bit 8 is the value of the condition code calculation which results in the branch being taken the low order byte is a signed word offset relative to the current location of the program counter this allows for forward and reverse branches in code 15 9 8 7 0 opcode c offset opcode c mnemonic condition or operation 000 1 br branch always pc pc 2 sign extend offset 001 0 bne branch if not equal z 0 001 1 beq branch if equal z 1 002 0 bge branch if greater than or equal n v 0 002 1 blt branch if less than n v 1 003 0 bgt branch if greater than z n v 0 003 1 ble branch if less than or equal z n v 1 100 0 bpl branch if plus n 0 100 1 bmi branch if minus n 1 101 0 bhi branch if higher c z 0 101 1 blos branch if lower or same c z 1 102 0 bvc branch if overflow clear v 0 102 1 bvs branch if overflow set v 1 103 0 bcc or bhis branch if carry clear or branch if higher or same c 0 103 1 bcs or blo branch if carry set or branch if lower c 1 the limited range of the branch instructions meant that as code grew the target addresses of some branches would become unreachable the programmer would change the one word br to the two word jmp instruction from the next group as jmp has no conditional forms the programmer would change beq to a bne that branched around a jmp sob subtract one and branch is another conditional branch instruction the specified register is decremented by 1 and if the result is not zero a reverse branch is taken based on the 6 bit word offset 15 9 8 6 5 0 opcode reg offset opcode mnemonic operation 077 sob subtract one and branch reg reg 1 if reg 0 then pc pc 2 offset subroutine instructions edit jsr calls a subroutine a group of six bits specifies the addressing mode the jsr instruction can save any register on the stack and load that register with the return address programs that do not need this feature specify pc as the register jsr pc address and the routine returns using rts pc if a routine is called with for instance jsr r4 address then the old value of r4 is pushed on the top of the stack and the address just after jsr ordinarily the return address is placed in r4 however the routine can gain access to values coded in line by specifying r4 or to in line pointers by specifying r4 the autoincrementation moves past these data to the point at which the caller s code resumes in either case such a routine specifies rts r4 to return to its caller the jsr pc sp form which exchanges the contents of pc with the top element of the stack can be used to implement coroutines once a routine places the entry address of the coroutine on the stack executing jsr pc sp saves pc on the stack and jumps to the coroutine both coroutines can then use additional jsr pc sp instructions to jump to the other coroutine wherever it left off this lets the two routines swap control and resume one another at the point of the previous swap 15 9 8 6 5 3 2 0 opcode reg src register opcode mnemonic operation 004 jsr jump to subroutine sp reg reg pc pc src the value of pc moved to reg is the address after the jsr instruction 15 3 2 0 opcode reg opcode mnemonic operation 00020 rts return from subroutine pc reg reg sp 15 6 5 0 opcode nn opcode mnemonic operation 0064 mark return from subroutine discard stack entries sp sp 2 x nn pc r5 r5 sp mark is used to delete parameters on the stack when exiting a subroutine mark is unusual in that it is placed on the return stack by the caller for later execution directly on the stack by the return routine first the caller pushes r5 on the stack next up to 63 word arguments may be placed on the stack the caller then adds the number of arguments to the mark opcode and pushes that result on the stack the value of sp is copied to r5 finally a jsr pc address is executed to call the subroutine after executing its code the subroutine terminates with an rts r5 this loads the value in r5 pointing to mark instruction on stack into the pc and pops the caller s return address into r5 the mark instruction is executed mark multiplies the number of arguments by 2 adds that to sp deleting the arguments and then returns to caller with the equivalent of an rts r5 the mark instruction is rarely used as its convoluted operation can be replaced by an add to sp 6 trap instructions edit 15 9 8 7 0 opcode s operation code opcode s mnemonic operation 104 0 emt emulator trap sp ps sp pc pc 30 ps 32 104 1 trap general trap sp ps sp pc pc 34 ps 36 15 0 opcode opcode mnemonic operation 000002 rti return from interrupt pc sp ps sp 000003 bpt breakpoint trap sp ps sp pc pc 14 ps 16 000004 iot i o trap sp ps sp pc pc 20 ps 22 000006 rtt return from trap pc sp ps sp trap and exception vector address assignments edit vector condition 000000 reserved 000004 illegal instruction bus error stack limit 000010 reserved instruction 000014 bpt instruction trace trap 000020 iot instruction 000024 power fail 000030 emt instruction 000034 trap instruction 000114 parity error 000244 floating point exception 000250 memory management fault miscellaneous instructions edit 15 0 opcode opcode mnemonic operation 000000 halt halt processor halt execution before next instruction 000001 wait wait for interrupt halt execution before next instruction resume execution at next interrupt handler 000005 reset reset unibus assert init on unibus for 10 ms all other devices reset to power up state 000240 nop no operation do nothing condition code operations edit 15 6 5 4 3 2 1 0 opcode 1 s n z v c opcode s mnemonic operation 0002 0 ccc clear condition codes clear codes according to n z v c bits 0002 1 scc set condition codes set codes according to n z v c bits the four condition codes in the processor status word psw are n indicating a negative value z indicating a zero equal condition v indicating an overflow condition and c indicating a carry condition instructions in this group were what digital called micro programmed a single bit in the instruction word referenced a single condition code the assembler did not define syntax to specify every combination but the symbols scc and ccc assembled an instruction that set or cleared respectively all four condition codes clearing or setting none of the condition codes opcodes 000240 and 000260 respectively could effectively be considered as no operation instructions in fact the nop mnemonic assembled into 000240 inconsistent instructions edit over the life of the pdp 11 subtle differences arose in the implementation of instructions and combinations of addressing modes though no implementation was regarded as correct the inconsistencies did not affect ordinary use of the pdp 11 for example in the instruction mov r5 r5 whether r5 is autodecremented before its value is used as the source varies among models 7 optional instruction sets edit extended instruction set eis edit the eis is an option for the 11 35 40 and 11 03 and was supplied as standard on newer processors mul div multiply and divide integer operand to register pair ash ashc arithmetic shift a register or a register pair for a positive number it will shift left and right for a negative one floating instruction set fis edit fis is an option for the pdp 11 35 40 and 11 03 single precision floats are operated on a stack addressed by a register operand the high order 13 bits specify the operation to be performed a three bit field specifies which register is used as the floating point operand stack pointer each float is two words and each floating point instruction operates on two floats returning one float as a result the selected stack pointer is incremented by a stride of 4 after each operation 15 3 2 0 opcode reg opcode mnemonic operation 07500 fadd floating add 4 rn 4 rn rn rn rn 4 07501 fsub floating subtract 4 rn 4 rn rn rn rn 4 07502 fmul floating multiply 4 rn 4 rn rn rn rn 4 07503 fdiv floating divide 4 rn 4 rn rn rn rn 4 floating point processor fpp edit this was the optional floating point processor option for 11 45 and most subsequent models full floating point operations on single or double precision operands selected by single double bit in floating point status register single precision floating point data format predecessor of ieee 754 format sign bit 8 bit exponent 23 bit mantissa with hidden bit 24 commercial instruction set cis edit the commercial instruction set known as cis or cis11 adds string and binary coded decimal bcd instructions used by cobol and dibol it was implemented by optional microcode in the 11 23 24 8 9 and by an add in module in the 11 44 10 and one version of the 11 74 citation needed strings are represented by two 16 bit integers stored in any two of the general purpose registers or as two 16 bit values in subsequent locations in memory one is designated n which is the length up to 64 kb and the other a which is a pointer to the start of the character data in memory together an n a pair indicates the location and length of the string 11 195 406 the string copy operations are movec movtc and movrc movec copies the character data in memory from the location indicated in one n a pair to the location in a second n a both in registers with a third register containing a fill character in its lower 8 bits and zeroes in its upper 8 bits moveci does the same but with the locations and fill character stored in memory locations instead of registers in all of the move instructions if the source is shorter than the destination the destination is padded with the fill character and if the source is longer it is truncated if either occurs the processor status flags are used to indicate this movrc movrci are similar but copy backwards to reverse the original string into the destination 11 409 movtc movtci translate characters during copy using a 256 byte lookup table the beginning of which is pointed to by another register in movtc or a 16 bit pointer in memory in movtci translations use the source string s character values as index numbers and copy the value in the translation table at that index into the destination string this can be used for ebcdic to ascii conversions by placing the corresponding ascii character code for the mapped ebcdic codes in the table the character e is character 69 in ascii and 197 in ebcdic so to convert ebcdic to ascii one would make a table of 256 bytes with a 69 in location 197 when movtc is called and sees a 197 in the original string it will look in location 197 of the table find the 97 and output that in the new string performing the conversion 11 456 458 string comparisons are handled by cmpc which sets the processor condition codes based on the results of comparing two strings locc finds the first occurrence of a character in a string while skpc searches for the first character that does not match used for trimming blanks at the start of strings for instance scanc and spanc are similar to locc and skpc but match any charac...