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elated changes upload file permanent link page information cite this page get shortened url switch to legacy parser print export download as pdf printable version in other projects wikidata item appearance move to sidebar hide from wikipedia the free encyclopedia stage of electronic circuit design placement is an essential step in electronic design automation the portion of the physical design flow that assigns exact locations for various circuit components within the chip s core area an inferior placement assignment will not only affect the chip s performance but might also make it non manufacturable by producing excessive wire length which is beyond available routing resources consequently a placer must perform the assignment while optimizing a number of objectives to ensure that a circuit meets its performance demands together the placement and routing steps of ic design are known as place and route a placer takes a given synthesized circuit netlist together with a technology library and produces a valid and ideally optimal layout of all of the cells in the netlist the layout is optimized according to the aforementioned objectives and ready for cell resizing and buffering a step essential for timing and signal integrity satisfaction clock tree synthesis and routing follow completing the physical design process in many cases parts of or the entire physical design flow are iterated a number of times until design closure is achieved application specifics edit in the case of application specific integrated circuits or asics the chip s core layout area comprises a number of fixed height rows with either some or no space between them each row consists of a number of sites which can be occupied by the circuit components a free site is a site that is not occupied by any component circuit components are either standard cells macro blocks or i o pads 1 standard cells have a fixed height equal to a row s height but have variable widths the width of a cell is an integral number of sites on the other hand blocks are typically larger than cells and have variable heights that can stretch a multiple number of rows 1 some blocks can have preassigned locations say from a previous floorplanning process which limit the placer s task to assigning locations for just the cells in this case the blocks are typically referred to by fixed blocks alternatively some or all of the blocks may not have preassigned locations in this case they have to be placed with the cells in what is commonly referred to as mixed mode placement in addition to asics placement remains important in gate array structures such as field programmable gate arrays fpgas here prefabricated transistors are typically arranged into cells known as configurable logic blocks clbs 2 that are then arranged in rows or arrays separated by routing channels 3 the placement process then optimally maps the design specified as a netlist onto a number of these clbs as fpgas grow significantly in size i e the number of clbs on a die it is typical that asic placement algorithms are lightly modified for use in fpgas 4 objectives and constraints edit placement is formulated as a constrained optimization problem in particular the clock cycle of a chip is determined by the delay of its longest path usually referred to as critical path delay given a performance specification usually a clock period target in nanoseconds a placer attempts to ensure that no path exists with delay exceeding the maximum specified delay this objective may not be satisfiable on all designs there may exist no placement at all which meets the designer s targeted delay other key constraints include avoiding overlaps between circuit components the instances in the netlist accounting for pre placed fixed macros such as srams there are usually multiple optimization objectives including total wire length the sum of the lengths of all the wires in the design half perimeter wire length hpwl for a set of nets half of the perimeter of the minimum bounding box that encloses those nets 5 routing congestion local congestion is the difference between the lengths of wires in a region and the length of routing tracks available in that region local values can be aggregated in several ways such as adding up the top 10 greatest values power dynamic switching power depends on wire lengths which in turn depend on component locations additionally it is desirable to finish the placement process quickly this is difficult given that most placement sub problems are known to be at least np hard 6 total wirelength is typically the primary objective of most existing placers and serves as a precursor to other optimizations because e g power and delay tend to grow with wire length total wire length determines the routing demand and whether it can be satisfied by the routing supply defined by available routing tracks however making wires very short sometimes leads to local routing demand exceeding local routing supply such situations often require routing detours which increase wire lengths and signal delays therefore after preliminary optimization of total wirelength it is also important to handle routing congestion most wire length metrics including hpwl are not differentiable 7 for this reason most modern placers do not optimize wire length directly but rather construct their objective functions as a differentiable approximation of wire length there are many approximations available 8 9 power minimization typically notes wires with greater switching activity factors and assigns greater priority to making them shorter when many hot components are placed nearby a hot spot may arise and lead to harmful temperature gradients in such cases components can be spread out typical methods edit placement is divided into global placement and detailed placement global placement introduces dramatic changes by distributing all the instances to appropriate locations in a global scale with minor overlaps allowed detailed placement shifts each instance to nearby legal location with very moderate layout change placement and overall design quality is most dependent on the global placement performance early techniques for placement of integrated circuits can be categorized as combinatorial optimization for ic designs with thousands or tens of thousands of components simulated annealing 10 methodologies such as timberwolf 11 exhibits the best results when ic designs grew to millions of components placement leveraged hypergraph partitioning 12 using nested partitioning frameworks such as capo 13 combinatorial methods directly prevent component overlaps but struggle with interconnect optimization at large scale they are typically stochastic and can produce very different results for the same input when launched multiple times analytical methods for global placement model interconnect length by a continuous function and minimize this function directly subject to component density constraints these methods run faster and scale better than combinatorial methods but do not prevent component overlaps and must be postprocessed by combinatorial methods for detailed placement quadratic placement is an early analytical method that models interconnect length by a quadratic function and uses high performance quadratic optimization techniques when it was developed it demonstrated competitive quality of results and also stability unlike combinatorial methods gordian 14 formulates the wirelength cost as a quadratic function while still spreading cells apart through recursive partitioning the algorithm 15 models placement density as a linear term into the quadratic cost function and solves the placement problem by pure quadratic programming a common enhancement is weighting each net by the inverse of its length on the previous iteration provided the process converges this minimizes an objective linear in the wirelength 16 the majority of modern quadratic placers kraftwerk 17 fastplace 18 simpl 19 follow this framework each with different heuristics on how to determine the linear density force there exist known analogies between quadratic placement and the classical mechanics problem of finding the minimum energy of a system of springs or the force equilibrium 20 in this case these placers are known as force directed placement algorithms nonlinear placement models wirelength by exponential nonlinear functions and density by local piece wise quadratic functions in order to achieve better accuracy thus quality improvement 21 follow up academic work includes aplace 22 and ntuplace 23 24 eplace 7 is a state of the art global placement algorithm it spreads instances apart by simulating an electrostatic field which minimizes quality overhead it maintains good performance by solving the underlying partial differential equations efficiently using a method based on the fast fourier transform replace a successor to this algorithm is used by the open source tool openroad to perform its global placement 25 in 2021 google brain reported their alphachip reinforcement learning based algorithm had improved results compared to classical techniques 26 however this result is quite controversial 27 28 29 as the paper does not contain head to head comparisons to existing placers and is difficult to replicate due to proprietary content at least one initially favorable commentary has been retracted upon further review 30 see also edit electronic design automation design flow eda integrated circuit design floorplan microelectronics place and route references edit 1 2 a kahng j lienig i markov j hu vlsi physical design from graph partitioning to timing closure springer 2022 doi 10 1007 978 90 481 9591 6 isbn 978 3 030 96414 6 pp 10 13 structure of an fpga digilent blog retrieved 2026 07 06 a kahng j lienig i markov j hu vlsi physical design from graph partitioning to timing closure springer 2022 doi 10 1007 978 90 481 9591 6 isbn 978 3 030 96414 6 pp 14 15 li wuxi lin yibo pan david z 2019 elfplace electrostatics based placement for large scale heterogeneous fpgas 2019 ieee acm international conference on computer aided design iccad pp 1 8 bibcode 2019ccad conf 57l doi 10 1109 iccad45719 2019 8942075 isbn 978 1 7281 2350 9 kahng andrew b lienig jens markov igor l hu jin 2022 global and detailed placement in kahng andrew b lienig jens markov igor l hu jin eds vlsi physical design from graph partitioning to timing closure cham springer international publishing pp 95 130 doi 10 1007 978 3 030 96415 3_4 isbn 978 3 030 96415 3 retrieved 2026 07 06 korte bernhard vygen jens 2008 combinatorial problems in chip design in grötschel martin katona gyula o h sági gábor eds building bridges between mathematics and computer science berlin heidelberg springer pp 333 368 doi 10 1007 978 3 540 85221 6_12 isbn 978 3 540 85221 6 retrieved 2026 07 09 1 2 j lu p chen c c chang l sha d j s huang c c teng and c k cheng 2014 eplace electrostatics based placement using nesterov s method proceedings of the design automation conference acm pp 1 6 cite conference cs1 maint multiple names authors list link hsu meng kai chang yao wen balabanov valeriy 2011 tsv aware analytical placement for 3d ic designs 2011 48th acm edac ieee design automation conference dac 664 669 us6301693b1 naylor william c donelly ross sha lu non linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer issued 2001 10 09 s kirkpatrick c d g jr and m p vecchi 1983 optimization by simulated annealing science 220 4598 671 680 bibcode 1983sci 220 671k doi 10 1126 science 220 4598 671 pmid 17813860 cite journal cs1 maint multiple names authors list link c sechen and a sangiovanni vincentelli 1986 timberwolf3 2 a new standard cell placement and global routing package proceedings of the design automation conference acm pp 432 439 george karypis rajat aggarwal vipin kumar and shashi shekhar 1997 multilevel hypergraph partitioning applications in vlsi domain proceedings of the design automation conference acm pp 526 529 cite conference cs1 maint multiple names authors list link caldwell a e kahng a b markov i l june 2000 can recursive bisection alone produce routable placements proceedings of the 37th design automation conference pp 477 482 doi 10 1109 dac 2000 855358 kleinhans j m sigl g johannes f m antreich k j march 1991 gordian vlsi placement by quadratic programming and slicing optimization ieee transactions on computer aided design of integrated circuits and systems 10 3 356 365 bibcode 1991itcad 10 356k doi 10 1109 43 67789 s2cid 15274014 h eisenmann and f m johannes 1998 generic global placement and floorplanning proceedings of the design automation conference acm pp 269 274 sigl georg konrad doll and frank m johannes 1991 analytical placement a linear or a quadratic objective function proceedings of the 28th acm ieee design automation conference acm pp 427 432 cite conference cs1 maint multiple names authors list link p spindler u schlichtmann and f m johannes 2008 kraftwerk2 a fast force directed quadratic placement approach using an accurate net model ieee transactions on computer aided design 27 8 1398 1411 bibcode 2008itcad 27 1398s doi 10 1109 tcad 2008 925783 s2cid 16054185 cite journal cs1 maint multiple names authors list link n viswanathan m pan and c chu 2007 fastplace3 0 a fast multilevel quadratic placement algorithm with placement congestion control proceedings of the asia south pacific design automation conference pp 135 140 cite conference cs1 maint multiple names authors list link kim m c lee d j markov i l january 2011 simpl an effective placement algorithm ieee transactions on computer aided design of integrated circuits and systems 31 1 50 60 citeseerx 10 1 1 187 1292 doi 10 1109 tcad 2011 2170567 s2cid 47293399 cite journal cite uses deprecated parameter citeseerx help chu chris 2009 placement electronic design automation elsevier pp 635 685 doi 10 1016 b978 0 12 374364 0 50018 7 isbn 978 0 12 374364 0 retrieved 2026 07 09 usa 6301693 w c naylor r donelly and l sha non linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer a b kahng s reda and q wang 2005 architecture and details of a high quality large scale analytical placer proceedings of the international conference on computer aided design pp 891 898 t c chen z w jiang t c hsu h c chen and y w chang 2008 ntuplace3 an analytical placer for large scale mixed size designs with preplaced blocks and density constraint pdf ieee transactions on computer aided design 27 7 1228 1240 bibcode 2008itcad 27 1228c doi 10 1109 tcad 2008 923063 s2cid 11912537 cite journal cs1 maint multiple names authors list link hsu meng kai chen yi fang huang chau chin chou sheng lin tzu hen chen tung chieh chang yao wen 2014 ntuplace4h a novel routability driven placement algorithm for hierarchical mixed size circuit designs ieee transactions on computer aided design of integrated circuits an...