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metallization shorts the base of the parasitic transistor to its emitter the source of the mosfet and thus prevents spurious latching this solution however creates a diode between the drain cathode and the source anode of the mosfet making it able to block current in only one direction body diodes may be utilized as freewheeling diodes for inductive loads in configurations such as h bridge or half bridge while these diodes usually have rather high forward voltage drop they can handle large currents and are sufficient in many applications reducing part count and thus device cost and board space to increase efficiency synchronous rectification is often used to minimize the amount of time that the body diode conducts current switching operation edit fig 4 location of the intrinsic capacitances of a power mosfet because of its unipolar nature the power mosfet can switch at very high speed indeed there is no need to remove minority carriers as with bipolar devices the only intrinsic limitation in commutation speed is due to the internal capacitances of the mosfet see figure 4 these capacitances must be charged or discharged when the transistor switches this can be a relatively slow process because the current that flows through the gate capacitances is limited by the external driver circuit this circuit will actually dictate the commutation speed of the transistor assuming the power circuit has sufficiently low inductance further information mosfet gate driver capacitances edit in the mosfet datasheets the capacitances are often named c iss input capacitance drain and source terminal shorted c oss output capacitance gate and source shorted and c rss reverse transfer capacitance source connected to ground the relationship between these capacitances and those described below is c i s s c g s c g d c o s s c g d c d s c r s s c g d displaystyle begin matrix c_ iss c_ gs c_ gd c_ oss c_ gd c_ ds c_ rss c_ gd end matrix where c gs c gd and c ds are respectively the gate to source gate to drain and drain to source capacitances see below manufacturers prefer to quote c iss c oss and c rss because they can be directly measured on the transistor however as c gs c gd and c ds are closer to the physical meaning they will be used in the remaining of this article gate to source capacitance edit the c gs capacitance is constituted by the parallel connection of c oxn c oxp and c oxm see figure 4 as the n and p regions are highly doped the two former capacitances can be considered as constant c oxm is the capacitance between the polysilicon gate and the metal source electrode so it is also constant therefore it is common practice to consider c gs as a constant capacitance i e its value does not depend on the transistor state gate to drain capacitance edit the c gd capacitance can be seen as the connection in series of two elementary capacitances the first one is the oxide capacitance c oxd constituted by the gate electrode the silicon dioxide and the top of the n epitaxial layer it has a constant value the second capacitance c gdj is caused by the extension of the space charge zone when the mosfet is in off state therefore it is dependent upon the drain to gate voltage from this the value of c gd is c g d c o x d c g d j v g d c o x d c g d j v g d displaystyle c_ gd frac c_ oxd times c_ gdj left v_ gd right c_ oxd c_ gdj left v_ gd right the width of the space charge region is given by 36 w g d j 2 ϵ s i v g d q n displaystyle w_ gdj sqrt frac 2 epsilon _ si v_ gd qn where ϵ s i displaystyle epsilon _ si is the permittivity of the silicon q is the electron charge and n is the doping level the value of c gdj can be approximated using the expression of the plane capacitor c g d j a g d ϵ s i w g d j displaystyle c_ gdj a_ gd frac epsilon _ si w_ gdj where a gd is the surface area of the gate drain overlap therefore it comes c g d j v g d a g d q ϵ s i n 2 v g d displaystyle c_ gdj left v_ gd right a_ gd sqrt frac q epsilon _ si n 2v_ gd it can be seen that c gdj and thus c gd is a capacitance whose value is dependent upon the gate to drain voltage as this voltage increases the capacitance decreases when the mosfet is in on state c gdj is shunted so the gate to drain capacitance remains equal to c oxd a constant value drain to source capacitance edit as the source metallization overlaps the p wells see figure 1 the drain and source terminals are separated by a p n junction therefore c ds is the junction capacitance this is a non linear capacitance and its value can be calculated using the same equation as for c gdj other dynamic elements edit equivalent circuit of a power mosfet including the dynamic elements capacitors inductors the parasitic resistors the body diode packaging inductances edit to operate the mosfet must be connected to the external circuit most of the time using wire bonding although alternative techniques are investigated these connections exhibit a parasitic inductance which is in no way specific to the mosfet technology but has important effects because of the high commutation speeds parasitic inductances tend to maintain their current constant and generate overvoltage during the transistor turn off resulting in increasing commutation losses a parasitic inductance can be associated with each terminal of the mosfet they have different effects the gate inductance has little influence assuming it is lower than some hundreds of nanohenries because the current gradients on the gate are relatively slow in some cases however the gate inductance and the input capacitance of the transistor can constitute an oscillator this must be avoided as it results in very high commutation losses up to the destruction of the device on a typical design parasitic inductances are kept low enough to prevent this phenomenon the drain inductance tends to reduce the drain voltage when the mosfet turns on so it reduces turn on losses however as it creates an overvoltage during turn off it increases turn off losses the source parasitic inductance has the same behaviour as the drain inductance plus a feedback effect that makes commutation last longer thus increasing commutation losses at the beginning of a fast turn on due to the source inductance the voltage at the source on the die will be able to jump up as well as the gate voltage the internal v gs voltage will remain low for a longer time therefore delaying turn on at the beginning of a fast turn off as current through the source inductance decreases sharply the resulting voltage across it goes negative with respect to the lead outside the package raising the internal v gs voltage keeping the mosfet on and therefore delaying turn off limits of operation edit gate oxide breakdown edit the gate oxide is very thin 100 nm or less so it can only sustain a limited voltage in the datasheets manufacturers often state a maximum gate to source voltage around 20 v and exceeding this limit can result in destruction of the component furthermore a high gate to source voltage reduces significantly the lifetime of the mosfet with little to no advantage on r dson reduction to deal with this issue a gate driver circuit is often used maximum drain to source voltage edit power mosfets have a maximum specified drain to source voltage in the off state beyond which breakdown may occur exceeding the breakdown voltage causes the device to conduct potentially damaging it and other circuit elements due to excessive power dissipation maximum drain current edit the drain current must generally stay below a certain specified value maximum continuous drain current it can reach higher values for very short durations of time maximum pulsed drain current sometimes specified for various pulse durations the drain current is limited by heating due to resistive losses in internal components such as bond wires and other phenomena such as electromigration in the metal layer maximum temperature edit the junction temperature t j of the mosfet must stay under a specified maximum value for the device to function reliably determined by mosfet die layout and packaging materials the packaging often limits the maximum junction temperature due to the molding compound and where used epoxy characteristics the maximum operating ambient temperature is determined by the power dissipation and thermal resistance the junction to case thermal resistance is intrinsic to the device and package the case to ambient thermal resistance is largely dependent on the board mounting layout heatsinking area and air fluid flow the type of power dissipation whether continuous or pulsed affects the maximum operating temperature due to thermal mass characteristics in general the lower the frequency of pulses for a given power dissipation the higher maximum operating ambient temperature due to allowing a longer interval for the device to cool down models such as a foster network can be used to analyze temperature dynamics from power transients safe operating area edit the safe operating area defines the combined ranges of drain current and drain to source voltage the power mosfet is able to handle without damage it is represented graphically as an area in the plane defined by these two parameters both drain current and drain to source voltage must stay below their respective maximum values but their product must also stay below the maximum power dissipation the device is able to handle thus the device cannot be operated at its maximum current and maximum voltage simultaneously 37 latch up edit the equivalent circuit for a power mosfet consists of one mosfet in parallel with a parasitic bjt if the bjt turns on it cannot be turned off since the gate has no control over it this phenomenon is known as latch up which can lead to device destruction the bjt can be turned on due to a voltage drop across the p type body region to avoid latch up the body and the source are typically short circuited within the device package technology edit this power mosfet has a meshed gate with square cells the gate layout of this mosfet is composed of parallel strips layout edit cellular structure edit as described above the current handling capability of a power mosfet is determined by its gate channel width the gate channel width is the third z axis dimension of the cross sections pictured to minimize cost and size it is valuable to keep the transistor s die area size as small as possible therefore optimizations have been developed to increase the width of the channel surface area i e increase the channel density they mainly consist of creating cellular structures repeated over the whole area of the mosfet die several shapes have been proposed for these cells the most famous being the hexagonal shape used in international rectifier s hexfet devices another way to increase the channel density is to reduce the size of the elementary structure this allows for more cells in a given surface area and therefore more channel width however as the cell size shrinks it becomes more difficult to ensure proper contact of every cell to overcome this a strip structure is often used see figure it is less efficient than a cellular structure of equivalent resolution in terms of channel density but can cope with smaller pitch another advantage of the planar stripe structure is that it is less susceptible to failure during avalanche breakdown events in which the parasitic bipolar transistor turns on from sufficient forward bias in the cellular structure if the source terminal of any one cell is poorly contacted then it becomes much more likely that the parasitic bipolar transistor latches on during an avalanche breakdown event because of this mosfets utilizing a planar stripe structure can only fail during avalanche breakdown due to extreme thermal stress 38 structures edit the vmos structure has a v groove at the gate region the umos has a trench gate it is intended to increase the channel density by making the channel vertical p substrate power mosfet edit a p substrate mosfet also called a p channel mosfet or pmos is a mosfet with opposite doping types n instead of p and p instead of n in the cross section in figure 1 this mosfet is made using a p type substrate with a p epitaxy as the channel sits in a n region this transistor is turned on by a negative gate to source voltage this makes it desirable in a buck converter where one of the terminals of the switch is connected to the high side of the input voltage with an n channel or nmos mosfet this configuration requires a gate voltage equal to v i n v g s displaystyle v_ in v_ gs whereas no voltage over v i n displaystyle v_ in is required with a p channel mosfet the main disadvantage of this type of mosfet is the inferior on state performance as it uses holes as charge carriers which have a much lower mobility than electrons as resistivity is directly related to mobility a given p channel device will have a r d s o n displaystyle r_ dson three times higher than an n channel mosfet with the same dimensions vmos edit the vmos structure has a v groove at the gate region and was used for the first commercial devices 39 umos edit in this power mosfet structure also called trench mos the gate electrode is buried in a trench etched in the silicon this results in a vertical channel the main interest of the structure is the absence of the jfet effect the name of the structure comes from the u shape of the trench super junction deep trench technology edit especially for voltages beyond 500 v some manufacturers including infineon technologies with its coolmos products have begun to use a charge compensation principle with this technology the resistance of the epitaxial layer which is the biggest contributor more than 95 to the device resistance of high voltage mosfets can be reduced by a factor of greater than 5 seeking to improve the manufacturing efficiency and reliability of super junction mosfets renesas electronics developed a super junction structure with a deep trench process technique this technology entails etching trenches in the low impurity n type material to form p type regions this process overcomes problems inherent to the multi level epitaxial growth approach and results in extremely low on resistance and reduced internal capacitance due to the increased p n junction area a super junction structure has a smaller reverse recovery time but larger reverse recovery current compared to a conventional planar power mosfet see also edit insulated gate bipolar transistor mosfet power electronics power semiconductor device references edit irlz24n 55v n channel power mosfet to 220ab package infineon irwin j david 1997 the industrial electronics handbook crc press p 218 isbn 9780849383434 1 2 3 power mosfet basics pdf alpha omega semiconductor retrieved 29 july 2019 1 2 duncan ben 1996 high performance audio power amplifiers elsevier pp 178 81 isbn 9780080508047 us2802760a lincoln derick frosch carl j oxidation of semiconductive surfaces for controlled diff...