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the (229), and (138), spi (132), slave (85), for (73), #master (70), serial (62), data (59), with (58), bus (55), from (53), edit (53), are (47), interface (44), devices (42), bit (41), clock (40), that (34), not (30), #peripheral (29), signal (27), may (26), espi (26), mode (26), using (25), this (25), can (25), single (24), pdf (23), protocol (23), slaves (23), used (22), some (22), high (22), retrieved (21), when (21), one (21), use (20), only (20), sclk (20), each (19), quad (19), original (19), memory (19), miso (19), low (19), have (19), out (19), different (19), support (18), which (18), its (18), all (17), wire (17), device (17), chip (17), such (17), bits (17), output (16), shift (16), mosi (16), standard (16), communication (16), flash (15), motorola (15), line (15), duplex (15), other (15), signals (15), has (14), chips (14), select (14), pins (14), intel (13), daisy (13), 2023 (13), archived (13), microwire (13), transmission (13), than (13), also (13), cycles (13), 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Text of the page (random words):
c touchscreens video game controllers control devices audio codecs digital potentiometers dacs camera lenses canon ef lens mount memory flash and eeproms any mmc or sd card including sdio variant note 3 real time clocks lcds sometimes even for managing image data shift registers for additional i o 8 9 board real estate and wiring savings compared to a parallel bus are significant and have earned spi a solid role in embedded systems that is true for most system on a chip processors both with higher end 32 bit processors such as those using arm mips or powerpc and with lower end microcontrollers such as the avr pic and msp430 these chips usually include spi controllers capable of running in either master or slave mode in system programmable avr controllers including blank ones can be programmed using spi 12 chip or fpga based designs sometimes use spi to communicate between internal components on chip real estate can be as costly as its on board cousin and for high performance systems fpgas sometimes use spi to interface as a slave to a host as a master to sensors or for flash memory used to bootstrap if they are sram based the full duplex capability makes spi very simple and efficient for single master single slave applications some devices use the full duplex mode to implement an efficient swift data stream for applications such as digital audio digital signal processing or telecommunications channels but most off the shelf chips stick to half duplex request response protocols variations edit spi implementations have a wide variety of protocol variations some devices are transmit only others are receive only slave selects are sometimes active high rather than active low some devices send the least significant bit first signal levels depend entirely on the chips involved and while the baseline spi protocol has no command codes every device may define its own protocol of command codes some variations are minor or informal while others have an official defining document and may be considered to be separate but related protocols original definition edit motorola in 1983 listed 13 three 6805 8 bit microcomputers that have an integrated serial peripheral interface whose functionality is described in a 1984 manual 14 an991 edit motorola s 1987 application node an991 using the serial peripheral interface to communicate between multiple microcomputers 15 now under nxp last revised 2002 5 informally serves as the official defining document for spi timing variations edit some devices have timing variations from motorola s cpol cpha modes sending data from slave to master may use the opposite clock edge as master to slave devices often require extra clock idle time before the first clock or after the last one or between a command and its response some devices have two clocks one to read data and another to transmit it into the device many of the read clocks run from the slave select line transmission size edit different transmission word sizes are common many spi chips only support messages that are multiples of 8 bits such chips can not interoperate with the jtag or sgpio protocols or any other protocol that requires messages that are not multiples of 8 bits no slave select edit some devices do not use slave select and instead manage protocol state machine entry exit using other methods connectors edit anyone needing an external connector for spi defines their own or uses another standard connection such as uext pmod various jtag connectors secure digital card socket etc flow control edit some devices require an additional flow control signal from slave to master indicating when data is ready this leads to a 5 wire protocol instead of the usual 4 such a ready or enable signal is often active low and needs to be enabled at key points such as after commands or between words without such a signal data transfer rates may need to be slowed down significantly or protocols may need to have dummy bytes inserted to accommodate the worst case for the slave response time examples include initiating an adc conversion addressing the right page of flash memory and processing enough of a command that device firmware can load the first word of the response many spi masters do not support that signal directly and instead rely on fixed delays safespi edit safespi 16 is an industry standard for spi in automotive applications its main focus is the transmission of sensor data between different devices high reliability modifications edit in electrically noisy environments since spi has few signals it can be economical to reduce the effects of common mode noise by adapting spi to use low voltage differential signaling 17 another advantage is that the controlled devices can be designed to loop back to test signal integrity 18 intelligent spi controllers edit a queued serial peripheral interface qspi different to but has same abbreviation as quad spi described in quad spi is a type of spi controller that uses a data queue to transfer data across an spi bus 19 it has a wrap around mode allowing continuous transfers to and from the queue with only intermittent attention from the cpu consequently the peripherals appear to the cpu as memory mapped parallel devices this feature is useful in applications such as control of an a d converter other programmable features in queued spi are chip selects and transfer length delay spi controllers from different vendors support different feature sets such direct memory access dma queues are not uncommon although they may be associated with separate dma engines rather than the spi controller itself such as used by multichannel buffered serial port mcbsp note 4 most spi master controllers integrate support for up to four slave selects note 5 although some require slave selects to be managed separately through gpio lines note that queued spi is different from quad spi and some processors even confusingly allow a single qspi interface to operate in either quad or queued mode 20 three wire edit three wire variants of spi restricted to a half duplex mode use a single bidirectional data line called siso slave out slave in or momi master out master in instead of spi s two unidirectional lines mosi and miso three wire tends to be used for lower performance parts such as small eeproms used only during system startup certain sensors and microwire few spi controllers support this mode although it can be easily bit banged in software bit width extensions edit dual spi edit for instances where the full duplex nature of spi is not used an extension uses both data pins in a half duplex configuration to send two bits per clock cycle typically a command byte is sent requesting a response in dual mode after which the mosi line becomes sio0 serial i o 0 and carries even bits while the miso line becomes sio1 and carries odd bits data is still transmitted most significant bit first but sio1 carries bits 7 5 3 and 1 of each byte while sio0 carries bits 6 4 2 and 0 this is particularly popular among spi roms which have to send a large amount of data and comes in two variants 21 22 dual read sends the command and address from the master in single mode and returns the data in dual mode dual i o sends the command in single mode then sends the address and return data in dual mode quad spi edit quad spi qspi different to but has same abbreviation as queued spi described in intelligent spi controllers goes beyond dual spi adding two more i o lines sio2 and sio3 and sends 4 data bits per clock cycle again it is requested by special commands which enable quad mode after the command itself is sent in single mode 21 22 sqi type 1 commands sent on single line but addresses and data sent on four lines sqi type 2 commands and addresses sent on a single line but data sent received on four lines qpi sqi edit further extending quad spi some devices support a quad everything mode where all communication takes place over 4 data lines including commands 23 this is variously called qpi 22 not to be confused with intel quickpath interconnect or serial quad i o sqi 24 this requires programming a configuration bit in the device and requires care after reset to establish communication double data rate edit in addition to using multiple lines for i o some devices increase the transfer rate by using double data rate transmission 25 26 sgpio edit main article sgpio sgpio is essentially another incompatible application stack for spi designed for particular backplane management activities citation needed sgpio uses 3 bit messages intel s enhanced serial peripheral interface edit intel has developed a successor to its low pin count lpc bus that it calls the enhanced serial peripheral interface espi bus intel aims to reduce the number of pins required on motherboards and increase throughput compared to lpc reduce the working voltage to 1 8 volts to facilitate smaller chip manufacturing processes allow espi peripherals to share spi flash devices with the host the lpc bus did not allow firmware hubs to be used by lpc peripherals tunnel previous out of band pins through espi and allow system designers to trade off cost and performance 27 28 an espi bus can either be shared with spi devices to save pins or be separate from an spi bus to allow more performance especially when espi devices need to use spi flash devices 27 this standard defines an alert signal that is used by an espi slave to request service from the master in a performance oriented design or a design with only one espi slave each espi slave will have its alert pin connected to an alert pin on the espi master that is dedicated to each slave allowing the espi master to grant low latency service because the espi master will know which espi slave needs service and will not need to poll all of the slaves to determine which device needs service in a budget design with more than one espi slave all of the alert pins of the slaves are connected to one alert pin on the espi master in a wired or connection which requires the master to poll all the slaves to determine which ones need service when the alert signal is pulled low by one or more peripherals that need service only after all of the devices are serviced will the alert signal be pulled high due to none of the espi slaves needing service and therefore pulling the alert signal low 27 this standard allows designers to use 1 bit 2 bit or 4 bit communications at speeds from 20 to 66 mhz to further allow designers to trade off performance and cost 27 communications that were out of band of lpc like general purpose input output gpio and system management bus smbus should be tunneled through espi via virtual wire cycles and out of band message cycles respectively in order to remove those pins from motherboard designs using espi 27 this standard supports standard memory cycles with lengths of 1 byte to 4 kilobytes of data short memory cycles with lengths of 1 2 or 4 bytes that have much less overhead compared to standard memory cycles and i o cycles with lengths of 1 2 or 4 bytes of data which are low overhead as well this significantly reduces overhead compared to the lpc bus where all cycles except for the 128 byte firmware hub read cycle spends more than one half of all of the bus s throughput and time in overhead the standard memory cycle allows a length of anywhere from 1 byte to 4 kilobytes in order to allow its larger overhead to be amortised over a large transaction espi slaves are allowed to initiate bus master versions of all of the memory cycles bus master i o cycles which were introduced by the lpc bus specification and isa style dma including the 32 bit variant introduced by the lpc bus specification are not present in espi therefore bus master memory cycles are the only allowed dma in this standard 27 espi slaves are allowed to use the espi master as a proxy to perform flash operations on a standard spi flash memory slave on behalf of the requesting espi slave 27 64 bit memory addressing is also added but is only permitted when there is no equivalent 32 bit address 27 the intel z170 chipset can be configured to implement either this bus or a variant of the lpc bus that is missing its isa style dma capability and is underclocked to 24 mhz instead of the standard 33 mhz 29 the espi bus is also adopted by amd ryzen chipsets interoperability with other standards edit microwire edit microwire 30 often spelled μwire is essentially a predecessor of spi and a trademark of national semiconductor it s a strict subset of spi half duplex and using spi mode 0 microwire chips tend to need slower clock rates than newer spi versions perhaps 2 mhz vs 20 mhz some microwire chips also support a three wire mode microwire plus edit microwire plus 31 is an enhancement of microwire and features full duplex communication and support for spi modes 0 and 1 there was no specified improvement in serial clock speed jtag edit main article jtag although there are some similarities between spi and the jtag ieee 1149 1 2013 protocol they are not interchangeable jtag is specifically intended to provide reliable test access to the i o pins from an off board controller with less precise signal delay and skew parameters while spi has many varied applications while not strictly a level sensitive interface the jtag protocol supports the recovery of both setup and hold violations between jtag devices by reducing the clock rate or changing the clock s duty cycles consequently the jtag interface is not intended to support extremely high data rates 32 development tools edit single board computers edit single board computers may provide pin access to spi hardware units for instance the raspberry pi s j8 header exposes at least two spi units that can be used via linux drivers or python usb to spi adapters edit there are a number of usb adapters that allow a desktop pc or smartphone with usb to communicate with spi chips e g ch341a b 33 based or ft 221xs 34 they are used for embedded systems chips fpga asic and soc and peripheral testing programming and debugging many of them also provide scripting or programming capabilities e g visual basic c c vhdl and can be used with open source programs like flashrom imsprog snander or avrdude for flash eeprom bootloader and bios programming the key spi parameters are the maximum supported frequency for the serial interface command to command latency and the maximum length for spi commands it is possible to find spi adapters on the market today that support up to 100 mhz serial interfaces with virtually unlimited access length spi protocol being a de facto standard some spi host adapters also have the ability of supporting other protocols beyond the traditional 4 wire spi for example support of quad spi protocol or other custom serial protocol that derive from spi 35 protocol analyzers edit main article logic analyzer logic analyzers are tools which collect timestamp analyze decode store and view the high speed waveforms to help debug and develop most logic ...