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temporal multithreading wikipedia jump to content main menu main menu move to sidebar hide navigation main page contents current events random article about wikipedia contact us contribute help learn to edit community portal recent changes upload file special pages search search appearance donate create account log in personal tools donate create account log in contents move to sidebar hide top 1 variations 2 comparison to simultaneous multithreading 3 see also 4 references toggle the table of contents temporal multithreading 5 languages فارسی 한국어 русский српски srpski українська edit links article talk english read edit view history tools tools move to sidebar hide actions read edit view history general what links here related changes upload file permanent link page information cite this page get shortened url switch to legacy parser print export download as pdf printable version in other projects wikidata item appearance move to sidebar hide from wikipedia the free encyclopedia concept in computer hardware this article needs more citations please help improve this article by adding citations to reliable sources unsourced material may be challenged and removed find sources temporal multithreading news newspapers books scholar jstor march 2016 learn how and when to remove this message temporal multithreading is one of the two main forms of multithreading that can be implemented on computer processor hardware the other being simultaneous multithreading the distinguishing difference between the two forms is the maximum number of concurrent threads that can execute in any given pipeline stage in a given cycle in temporal multithreading the number is one while in simultaneous multithreading the number is greater than one some authors use the term superthreading synonymously 1 variations edit there are many possible variations of temporal multithreading but most can be classified into two sub forms coarse grained the main processor pipeline contains only one thread at a time the processor must effectively perform a rapid context switch before executing a different thread this fast context switch is sometimes referred to as a thread switch there may or may not be additional penalty cycles when switching there are many possible variations of coarse grained temporal multithreading mainly concerning the algorithm that determines when thread switching occurs this algorithm may be based on one or more of many different factors including cycle counts cache misses and fairness fine grained or interleaved the main processor pipeline may contain multiple threads with context switches effectively occurring between pipe stages e g in the barrel processor this form of multithreading can be more expensive than the coarse grained forms because execution resources that span multiple pipe stages may have to deal with multiple threads also contributing to cost is the fact that this design cannot be optimized around the concept of a background thread any of the concurrent threads implemented by the hardware might require its state to be read or written on any cycle 2 comparison to simultaneous multithreading edit in any of its forms temporal multithreading is similar in many ways to simultaneous multithreading as in the simultaneous process the hardware must store a complete set of states per concurrent thread implemented the hardware must also preserve the illusion that a given thread has the processor resources to itself fairness algorithms must be included in both types of multithreading situations to prevent one thread from dominating processor time and or resources temporal multithreading has an advantage over simultaneous multithreading in that it causes lower processor heat output however it allows only one thread to be executed at a time see also edit barrel processor symmetric multiprocessing references edit stokes jon october 3 2002 introduction to multithreading superthreading and hyperthreading ars technica superthreading with a multithreaded processor silberschatz abraham 2012 operating system concepts wiley 9th edition p 283 isbn 978 1118063330 v t e processor technologies models abstract machine stored program computer finite state machine with datapath hierarchical deterministic finite automaton queue automaton cellular automaton quantum cellular automaton turing machine alternating turing machine universal post turing quantum nondeterministic turing machine probabilistic turing machine hypercomputation zeno machine belt machine stack machine register machines counter pointer random access random access stored program architecture microarchitecture von neumann harvard modified dataflow transport triggered cellular endianness memory access numa huma load store register memory cache hierarchy memory hierarchy virtual memory secondary storage heterogeneous fabric multiprocessing cognitive neuromorphic instruction set architectures types orthogonal instruction set cisc risc application specific edge trips vliw epic misc oisc nisc zisc visc architecture quantum computing comparison addressing modes instruction sets motorola 68000 series vax pdp 11 x86 arm stanford mips mips mips x power power powerpc power isa clipper architecture sparc superh dec alpha etrax cris m32r unicore itanium openrisc risc v microblaze lmc system 3x0 s 360 s 370 s 390 z architecture tilera isa visc architecture epiphany architecture others execution instruction pipelining pipeline stall operand forwarding classic risc pipeline hazards data dependency structural control false sharing out of order scoreboarding tomasulo s algorithm reservation station re order buffer register renaming wide issue speculative branch prediction memory dependence prediction parallelism level bit bit serial word instruction pipelining scalar superscalar task thread process data vector memory distributed multithreading temporal simultaneous hyperthreading simultaneous and heterogenous speculative preemptive cooperative flynn s taxonomy sisd simd array processing simt pipelined processing associative processing swar misd mimd spmd processor performance transistor count instructions per cycle ipc cycles per instruction cpi instructions per second ips floating point operations per second flops transactions per second tps synaptic updates per second sups performance per watt ppw cache performance metrics computer performance by orders of magnitude types central processing unit cpu graphics processing unit gpu gpgpu vector barrel stream tile processor coprocessor pal asic fpga fpoa cpld multi chip module mcm system in a package sip package on a package pop by application embedded system microprocessor microcontroller mobile ultra low voltage asip soft microprocessor systems on chip system on a chip soc multiprocessor mpsoc cypress psoc network on a chip noc hardware accelerators coprocessor ai accelerator graphics processing unit gpu image processor vision processing unit vpu physics processing unit ppu digital signal processor dsp tensor processing unit tpu secure cryptoprocessor network processor baseband processor word size 1 bit 4 bit 8 bit 12 bit 15 bit 16 bit 24 bit 32 bit 48 bit 64 bit 128 bit 256 bit 512 bit bit slicing others variable core count single core multi core manycore heterogeneous architecture components core cache cpu cache scratchpad memory data cache instruction cache replacement policies coherence bus clock rate clock signal fifo functional units arithmetic logic unit alu address generation unit agu floating point unit fpu memory management unit mmu load store unit translation lookaside buffer tlb branch predictor branch target predictor integrated memory controller imc memory management unit instruction decoder logic combinational sequential glue logic gate quantum array registers processor register status register stack register register file memory buffer memory address register program counter control unit hardwired control unit instruction unit data buffer write buffer microcode rom counter datapath multiplexer demultiplexer adder multiplier cpu binary decoder address decoder sum addressed decoder barrel shifter circuitry integrated circuit 3d mixed signal power management boolean digital analog quantum switch power management pmu apm acpi dynamic frequency scaling dynamic voltage scaling clock gating performance per watt ppw related history of general purpose cpus microprocessor chronology processor design digital electronics hardware security module semiconductor device fabrication tick tock model pin grid array chip carrier v t e parallel computing general distributed computing parallel computing parallel algorithm massively parallel cloud computing high performance computing multiprocessing manycore processor gpgpu computer network systolic array levels bit instruction thread task data memory loop pipeline multithreading temporal simultaneous smt simultaneous and heterogenous speculative spmt preemptive cooperative clustered multi thread cmt hardware scout theory pram model pem model analysis of parallel algorithms amdahl s law gustafson s law cost efficiency karp flatt metric slowdown speedup elements process thread fiber instruction window array coordination multiprocessing memory coherence cache coherence cache invalidation barrier synchronization application checkpointing programming stream processing dataflow programming models implicit parallelism explicit parallelism concurrency non blocking algorithm hardware flynn s taxonomy sisd simd array processing simt pipelined processing associative processing misd mimd dataflow architecture pipelined processor superscalar processor vector processor multiprocessor symmetric asymmetric memory shared distributed distributed shared uma numa coma massively parallel computer computer cluster beowulf cluster grid computer hardware acceleration apis ateji px boost chapel hpx charm cilk coarray fortran cuda dryad c amp global arrays gpuopen mpi openmp opencl openhmpp openacc parallel extensions pvm pthreads raftlib rocm upc tbb zpl problems automatic parallelization cache stampede deadlock deterministic algorithm embarrassingly parallel parallel slowdown race condition software lockout scalability starvation category parallel computing retrieved from https en wikipedia org w index php title temporal_multithreading oldid 1350399315 categories flynn s taxonomy threads computing central processing unit computer architecture hidden categories articles with short description short description matches wikidata articles needing additional references from march 2016 all articles needing additional references this page was last edited on 21 april 2026 at 18 55 utc page was rendered with parsoid text is available under the creative commons attribution sharealike 4 0 license additional terms may apply by using this site you agree to the terms of use and privacy policy wikipedia is a registered trademark of the wikimedia foundation inc a non profit organization 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