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coa skip to main skip to sidebar coa saturday december 14 2013 i o system characteristics the dependability is important especially for storage devices performance measures latency response time throughput bandwidth desktops and embedded systems for response time and diversity of device servers dependability the system dependability is and to plan the time and resources needed to complete the case interconnecting component must have interconnections between cpu memory i o controllers bus shared communication channel parallel set of wires for data and synchronization of data transfer can become a bottleneck performance limited by physical factors wire length number of connections more recent alternative high speed serial connections with switches like networks bus types processor memory buses must short high speed and design is matched to memory organization i o buses longer allowing multiple connections specified by standards for interoperability connect to processor memory bus through a bridge bus synchronization a bus can be classified as synchronous or asynchronous the time for any transaction over a synchronous bus is known in advance in accepting and or generating information over the bus devices take the transaction time into account asynchronous bus on the other hand depends on the availability of data and the readiness of devices to initiate bus transactions in a single bus multiprocessor system bus arbitration is required in order to resolve the bus contention that takes place when more than one processor competes to access the bus the bus arbitration logic decides using a certain priority scheme which processor will be granted access to the bus during a certain time interval bus master random priority simple rotating priority after each arbitration cycle all priority levels are reduced one place with the lowest priority processor taking the highest priority equal priority when two or more requests are made there is equal chance of any one request being processed least recently used lru priority the highest priority is given to the processor that has not used the bus for the longest time the process of passing bus master ship from one processor to another is called handshaking and requires the use of two control signals bus request and bus grant the first indicates that a given processor is requesting master ship of the bus the second indicates that bus master ship is granted a third signal called bus busy is usually used to indicate whether or not the bus is currently being used published by siti nurhastini binti rosali b031310320 posted by unknown at 8 44 pm 1 comment email this blogthis share to x share to facebook share to pinterest input output introduction input output devices input devices input devices are devices used to input data or information into a computer for example scanner keyboard mouse joystick etc output devices output device is any electronic or electromechanical equipment connected to a computer and used to transfer data out of the computer for example speaker monitor floppy disk printer etc i o devices can be roughly categorized as storage communications user interface and other i o devices can be characterized by behavior partner data storage i o bus connection i o bus connection is bus that connects the cpu to main memory on the motherboard i o buses which connect the cpu with the systems other components branch off of the system bus input output module input output module is t he part of a modular which input and output devices are connected such as interface to cpu and memory interface to one or more peripherals function of input output module control and timing cpu ask i o module check status attached device then i o module tell the status after that if device already cpu request for data transfer lastly i o module gathers the data and transfers to the cpu cpu communicating can use command decoding data status reporting and address recognition for the devices connected to it device communication involves command status information and data transfer data buffering to overcome speed mismatch error detection allow detecting such errors like paper jam bad data etc published by syaqira liyana binti ahmad ghazali b031310568 posted by unknown at 5 57 am no comments email this blogthis share to x share to facebook share to pinterest data representation we must understand how data is represented by a computer in a view of mips programming language character representation a byte we have 8 bits a character is actually represent one byte in american standard code for information interchange ascii it offered 8 bit byte to represent character here is a section of an assembly language program to assemble the ascii bit patterns asciiz xyz xyz here are the bit patterns that the assembler will produce in the object module 58 59 5a 20 78 79 7a 00 binary dec hex abbr 000 0000 0 00 nul 000 0001 1 01 soh 000 0010 2 02 stx 000 0011 3 03 etx 000 0100 4 04 eot 000 0101 5 05 enq 000 0110 6 06 ack 000 0111 7 07 bel 000 1000 8 08 bs 000 1001 9 09 ht 000 1010 10 0a lf 000 1011 11 0b vt 000 1100 12 0c ff 000 1101 13 0d cr 000 1110 14 0e so 000 1111 15 0f si 001 0000 16 10 dle 001 0001 17 11 dc1 001 0010 18 12 dc2 001 0011 19 13 dc3 001 0100 20 14 dc4 001 0101 21 15 nak 001 0110 22 16 syn 001 0111 23 17 etb 001 1000 24 18 can 001 1001 25 19 em 001 1010 26 1a sub 001 1011 27 1b esc 001 1100 28 1c fs 001 1101 29 1d gs 001 1110 30 1e rs 001 1111 31 1f us 111 1111 127 7f del binary dec hex glyph 010 0000 32 20 010 0001 33 21 010 0010 34 22 010 0011 35 23 010 0100 36 24 010 0101 37 25 010 0110 38 26 010 0111 39 27 010 1000 40 28 010 1001 41 29 010 1010 42 2a 010 1011 43 2b 010 1100 44 2c 010 1101 45 2d 010 1110 46 2e 010 1111 47 2f 011 0000 48 30 0 011 0001 49 31 1 011 0010 50 32 2 011 0011 51 33 3 011 0100 52 34 4 011 0101 53 35 5 011 0110 54 36 6 011 0111 55 37 7 011 1000 56 38 8 011 1001 57 39 9 011 1010 58 3a 011 1011 59 3b 011 1100 60 3c 011 1101 61 3d 011 1110 62 3e 011 1111 63 3f binary dec hex glyph 100 0000 64 40 100 0001 65 41 a 100 0010 66 42 b 100 0011 67 43 c 100 0100 68 44 d 100 0101 69 45 e 100 0110 70 46 f 100 0111 71 47 g 100 1000 72 48 h 100 1001 73 49 i 100 1010 74 4a j 100 1011 75 4b k 100 1100 76 4c l 100 1101 77 4d m 100 1110 78 4e n 100 1111 79 4f o 101 0000 80 50 p 101 0001 81 51 q 101 0010 82 52 r 101 0011 83 53 s 101 0100 84 54 t 101 0101 85 55 u 101 0110 86 56 v 101 0111 87 57 w 101 1000 88 58 x 101 1001 89 59 y 101 1010 90 5a z 101 1011 91 5b 101 1100 92 5c 101 1101 93 5d 101 1110 94 5e 101 1111 95 5f _ binary dec hex glyph 110 0000 96 60 110 0001 97 61 a 110 0010 98 62 b 110 0011 99 63 c 110 0100 100 64 d 110 0101 101 65 e 110 0110 102 66 f 110 0111 103 67 g 110 1000 104 68 h 110 1001 105 69 i 110 1010 106 6a j 110 1011 107 6b k 110 1100 108 6c l 110 1101 109 6d m 110 1110 110 6e n 110 1111 111 6f o 111 0000 112 70 p 111 0001 113 71 q 111 0010 114 72 r 111 0011 115 73 s 111 0100 116 74 t 111 0101 117 75 u 111 0110 118 76 v 111 0111 119 77 w 111 1000 120 78 x 111 1001 121 79 y 111 1010 122 7a z 111 1011 123 7b 111 1100 124 7c 111 1101 125 7d 111 1110 126 7e number representation although computers operate on binary numbers in mips number is represented in decimal system or hexadecimal system when you need to insert number into a register you have to remember what kind of number system that you want to write in the program for example to load number 16 into register 5 we have two ways to represent decimal 16 in mips 1 ori 5 0 16 load number 16 into register 5 2 ori 5 0 0x10 load number 16 into register 5 published by siti nurhastini binti rosali b031310320 posted by unknown at 1 36 am 1 comment email this blogthis share to x share to facebook share to pinterest older posts home subscribe to posts atom intro we hope this blog can make people understanding on that topic we going to post feel free to leave any comments suggestions feedback s in the comments box thank you followers chat box view shoutbox knowledege 2013 16 december 9 i o input output introduction data representation multiplexer mips and qtspim simulator introduction to mips r2000 mips instruction format and addressing mode sequential logic digital logic november 7 total pageviews copyright 2013 by bits student sig2