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ores typically feature very long instruction word vliw and single instruction multiple data simd instruction set architectures and are therefore highly amenable to exploiting instruction level parallelism through parallel processing and superscalar execution 12 4 dsp cores most often feature application specific instructions and as such are typically application specific instruction set processors asip such application specific instructions correspond to dedicated hardware functional units that compute those instructions typical dsp instructions include multiply accumulate fast fourier transform fused multiply add and convolutions other edit as with other computer systems socs require timing sources to generate clock signals control execution of soc functions and provide time context to signal processing applications of the soc if needed popular time sources are crystal oscillators and phase locked loops soc peripherals including counter timers real time timers and power on reset generators socs also include voltage regulators and power management circuits intermodule communication edit socs comprise many execution units these units must often send data and instructions back and forth because of this all but the most trivial socs require communications subsystems originally as with other microcomputer technologies data bus architectures were used but recently designs based on sparse intercommunication networks known as networks on chip noc have risen to prominence and are forecast to overtake bus architectures for soc design in the near future 13 bus based communication edit historically a shared global computer bus typically connected the different components also called blocks of the soc 13 a very common bus for soc communications is arm s royalty free advanced microcontroller bus architecture amba standard direct memory access controllers route data directly between external interfaces and soc memory bypassing the cpu or control unit thereby increasing the data throughput of the soc this is similar to some device drivers of peripherals on component based multi chip module pc architectures computer buses are limited in scalability supporting only up to tens of cores multicore on a single chip 13 xiii wire delay is not scalable due to continued miniaturization system performance does not scale with the number of cores attached the soc s operating frequency must decrease with each additional core attached for power to be sustainable and long wires consume large amounts of electrical power these challenges are prohibitive to supporting manycore systems on chip 13 xiii network on a chip edit main article network on a chip in the late 2010s a trend of socs implementing communications subsystems in terms of a network like topology instead of bus based protocols has emerged a trend towards more processor cores on socs has caused on chip communication efficiency to become one of the key factors in determining the overall system performance and cost 13 xiii this has led to the emergence of interconnection networks with router based packet switching known as networks on chip nocs to overcome the bottlenecks of bus based networks 13 xiii networks on chip have advantages including destination and application specific routing greater power efficiency and reduced possibility of bus contention network on chip architectures take inspiration from communication protocols like tcp and the internet protocol suite for on chip communication 13 although they typically have fewer network layers optimal network on chip network architectures are an ongoing area of much research interest noc architectures range from traditional distributed computing network topologies such as torus hypercube meshes and tree networks to genetic algorithm scheduling to randomized algorithms such as random walks with branching and randomized time to live ttl many soc researchers consider noc architectures to be the future of soc design because they have been shown to efficiently meet power and throughput needs of soc designs current noc architectures are two dimensional 2d ic design has limited floorplanning choices as the number of cores in socs increase so as three dimensional integrated circuits 3dics emerge soc designers are looking towards building three dimensional on chip networks known as 3dnocs 13 design flow edit this section needs additional citations for verification please help improve this article by adding citations to reliable sources unsourced material may be challenged and removed march 2017 learn how and when to remove this template message main articles electronics design flow physical design electronics and platform based design see also systems design and software design process soc design flow a system on a chip consists of both the hardware described in structure and the software controlling the microcontroller microprocessor or digital signal processor cores peripherals and interfaces the design flow for an soc aims to develop this hardware and software at the same time also known as architectural co design the design flow must also take into account optimizations optimization goals and constraints most socs are developed from pre qualified hardware component ip core specifications for the hardware elements and execution units collectively blocks described above together with software device drivers that may control their operation of particular importance are the protocol stacks that drive industry standard interfaces like usb the hardware blocks are put together using computer aided design tools specifically electronic design automation tools the software modules are integrated using a software integrated development environment socs components are also often designed in high level programming languages such as c matlab or systemc and converted to rtl designs through high level synthesis hls tools such as c to hdl or flow to hdl 14 hls products called algorithmic synthesis allow designers to use c to model and synthesize system circuit software and verification levels all in one high level language commonly known to computer engineers in a manner independent of time scales which are typically specified in hdl 15 other components can remain software and be compiled and embedded onto soft core processors included in the soc as modules in hdl as ip cores once the architecture of the soc has been defined any new hardware elements are written in an abstract hardware description language termed register transfer level rtl which defines the circuit behavior or synthesized into rtl from a high level language through high level synthesis these elements are connected together in a hardware description language to create the full soc design the logic specified to connect these components and convert between possibly different interfaces provided by different vendors is called glue logic design verification edit further information functional verification and signoff electronic design automation chips are verified for validation correctness before being sent to a semiconductor foundry this process is called functional verification and it accounts for a significant portion of the time and energy expended in the chip design life cycle often quoted as 70 16 17 with the growing complexity of chips hardware verification languages like systemverilog systemc e and openvera are being used bugs found in the verification stage are reported to the designer traditionally engineers have employed simulation acceleration emulation or prototyping on reprogrammable hardware to verify and debug hardware and software for soc designs prior to the finalization of the design known as tape out field programmable gate arrays fpgas are favored for prototyping socs because fpga prototypes are reprogrammable allow debugging and are more flexible than application specific integrated circuits asics 18 19 with high capacity and fast compilation time simulation acceleration and emulation are powerful technologies that provide wide visibility into systems both technologies however operate slowly on the order of mhz which may be significantly slower up to 100 times slower than the soc s operating frequency acceleration and emulation boxes are also very large and expensive at over us 1 million citation needed fpga prototypes in contrast use fpgas directly to enable engineers to validate and test at or close to a system s full operating frequency with real world stimuli tools such as certus 20 are used to insert probes in the fpga rtl that make signals available for observation this is used to debug hardware firmware and software interactions across multiple fpgas with capabilities similar to a logic analyzer in parallel the hardware elements are grouped and passed through a process of logic synthesis during which performance constraints such as operational frequency and expected signal delays are applied this generates an output known as a netlist describing the design as a physical circuit and its interconnections these netlists are combined with the glue logic connecting the components to produce the schematic description of the soc as a circuit which can be printed onto a chip this process is known as place and route and precedes tape out in the event that the socs are produced as application specific integrated circuits asic optimization goals edit socs must optimize power use area on die communication positioning for locality between modular units and other factors optimization is necessarily a design goal of socs if optimization was not necessary the engineers would use a multi chip module architecture without accounting for the area use power consumption or performance of the system to the same extent common optimization targets for soc designs follow with explanations of each in general optimizing any of these quantities may be a hard combinatorial optimization problem and can indeed be np hard fairly easily therefore sophisticated optimization algorithms are often required and it may be practical to use approximation algorithms or heuristics in some cases additionally most soc designs contain multiple variables to optimize simultaneously so pareto efficient solutions are sought after in soc design oftentimes the goals of optimizing some of these quantities are directly at odds further adding complexity to design optimization of socs and introducing trade offs in system design for broader coverage of trade offs and requirements analysis see requirements engineering targets edit power consumption edit socs are optimized to minimize the electrical power used to perform the soc s functions most socs must use low power soc systems often require long battery life such as smartphones can potentially spend months or years without a power source while needing to maintain autonomous function and often are limited in power use by a high number of embedded socs being networked together in an area additionally energy costs can be high and conserving energy will reduce the total cost of ownership of the soc finally waste heat from high energy consumption can damage other circuit components if too much heat is dissipated giving another pragmatic reason to conserve energy the amount of energy used in a circuit is the integral of power consumed with respect to time and the average rate of power consumption is the product of current by voltage equivalently by ohm s law power is current squared times resistance or voltage squared divided by resistance p i v v 2 r i 2 r displaystyle p iv frac v 2 r i 2 r socs are frequently embedded in portable devices such as smartphones gps navigation devices digital watches including smartwatches and netbooks customers want long battery lives for mobile computing devices another reason that power consumption must be minimized in socs multimedia applications are often executed on these devices including video games video streaming image processing all of which have grown in computational complexity in recent years with user demands and expectations for higher quality multimedia computation is more demanding as expectations move towards 3d video at high resolution with multiple standards so socs performing multimedia tasks must be computationally capable platform while being low power to run off a standard mobile battery 12 3 performance per watt edit see also green computing socs are optimized to maximize power efficiency in performance per watt maximize the performance of the soc given a budget of power usage many applications such as edge computing distributed processing and ambient intelligence require a certain level of computational performance but power is limited in most soc environments the arm architecture has greater performance per watt than x86 in embedded systems so it is preferred over x86 for most soc applications requiring an embedded processor waste heat edit main article heat generation in integrated circuits see also thermal management in electronics and thermal design power soc designs are optimized to minimize waste heat output on the chip as with other integrated circuits heat generated due to high power density are the bottleneck to further miniaturization of components 21 1 the power densities of high speed integrated circuits particularly microprocessors and including socs have become highly uneven too much waste heat can damage circuits and erode reliability of the circuit over time high temperatures and thermal stress negatively impact reliability stress migration decreased mean time between failures electromigration wire bonding metastability and other performance degradation of the soc over time 21 2 9 in particular most socs are in a small physical area or volume and therefore the effects of waste heat are compounded because there is little room for it to diffuse out of the system because of high transistor counts on modern devices oftentimes a layout of sufficient throughput and high transistor density is physically realizable from fabrication processes but would result in unacceptably high amounts of heat in the circuit s volume 21 1 these thermal effects force soc and other chip designers to apply conservative design margins creating less performant devices to mitigate the risk of catastrophic failure due to increased transistor densities as length scales get smaller each process generation produces more heat output than the last compounding this problem soc architectures are usually heterogeneous creating spatially inhomogeneous heat fluxes which cannot be effectively mitigated by uniform passive cooling 21 1 throughput edit this section needs expansion you can help by adding to it october 2018 socs are optimized to maximize computational and communications throughput latency edit this section needs expansion you can help by adding to it october 2018 socs are optimized to minimize latency for some or all of their functions this can be accomplished by laying out elements with proper proximity and locality to each oth...