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hybrid memory cube wikipedia 86 captures 10 jan 2014 05 jul 2026 mar apr may 13 2022 2023 2024 success fail about this capture timestamps the wayback machine http web archive org web 20230413213247 https en wikipedia org wiki hybrid_memory_cube jump to content main menu main menu move to sidebar hide navigation main page contents current events random article about wikipedia contact us donate contribute help learn to edit community portal recent changes upload file languages language links are at the top of the page across from the title search create account log in personal tools create account log in pages for logged out editors learn more contributions talk contents move to sidebar hide top 1 overview 2 see also 3 references 4 external links toggle the table of contents toggle the table of contents hybrid memory cube 6 languages čeština français nederlands română русский türkçe edit links article talk english read edit view history tools tools move to sidebar hide actions read edit view history general what links here related changes upload file special pages permanent link page information cite this page wikidata item print export download as pdf printable version from wikipedia the free encyclopedia hybrid memory cube hmc is a high performance computer random access memory ram interface for through silicon vias tsv based stacked dram memory competing with the incompatible rival interface high bandwidth memory hbm overview edit hybrid memory cube was co developed by samsung electronics and micron technology in 2011 1 and announced by micron in september 2011 2 it promised a 15 times speed improvement over ddr3 3 the hybrid memory cube consortium hmcc is backed by several major technology companies including samsung micron technology open silicon arm hp since withdrawn microsoft since withdrawn altera acquired by intel in late 2015 and xilinx 4 5 micron while continuing to support hmcc is discontinuing the hmc product 6 in 2018 when it failed to achieve market adoption hmc combines through silicon vias tsv and microbumps to connect multiple currently 4 to 8 dies of memory cell arrays on top of each other 7 the memory controller is integrated as a separate die 2 hmc uses standard dram cells but it has more data banks than classic dram memory of the same size the hmc interface is incompatible with current ddr n ddr2 or ddr3 and competing high bandwidth memory implementations 8 hmc technology won the best new technology award from the linley group publisher of microprocessor report magazine in 2011 9 10 the first public specification hmc 1 0 was published in april 2013 11 according to it the hmc uses 16 lane or 8 lane half size full duplex differential serial links with each lane having 10 12 5 or 15 gbit s serdes 12 each hmc package is named a cube and they can be chained in a network of up to 8 cubes with cube to cube links and some cubes using their links as pass through links 13 a typical cube package with 4 links has 896 bga pins and a size of 31 31 3 8 millimeters 14 the typical raw bandwidth of a single 16 lane link with 10 gbit s signalling implies a total bandwidth of all 16 lanes of 40 gb s 20 gb s transmit and 20 gb s receive cubes with 4 and 8 links are planned though the hmc 1 0 spec limits link speed to 10 gbit s in the 8 link case therefore a 4 link cube can reach 240 gb s memory bandwidth 120 gb s each direction using 15 gbit s serdes while an 8 link cube can reach 320 gb s bandwidth 160 gb s each direction using 10 gbit s serdes 15 effective memory bandwidth utilization varies from 33 to 50 for smallest packets of 32 bytes and from 45 to 85 for 128 byte packets 7 as reported at the hotchips 23 conference in 2011 the first generation of hmc demonstration cubes with four 50 nm dram memory dies and one 90 nm logic die with total capacity of 512 mb and size 27 27 mm had power consumption of 11 w and was powered with 1 2 v 7 engineering samples of second generation hmc memory chips were shipped in september 2013 by micron 3 samples of 2 gb hmc stack of 4 memory dies each of 4 gbit are packed in a 31 31 mm package and have 4 hmc links other samples from 2013 have only two hmc links and a smaller package 16 19 5 mm 16 the second version of the hmc specification was published on 18 november 2014 by hmcc 17 hmc2 offers a variety of serdes rates ranging from 12 5 gbit s to 30 gbit s yielding an aggregate link bandwidth of 480 gb s 240 gb s each direction though promising only a total dram bandwidth of 320 gb sec 18 a package may have either 2 or 4 links down from the 4 or 8 in hmc1 and a quarter width option is added using 4 lanes the first processor to use hmcs was the fujitsu sparc64 xifx 19 which is used in the fujitsu primehpc fx100 supercomputer introduced in 2015 jedec s wide i o and wide i o 2 are seen as the mobile computing counterparts to the desktop server oriented hmc in that both involve 3d die stacks 20 in august 2018 micron announced a move away from hmc to pursue competing high performance memory technologies such as gddr6 and hbm 21 see also edit mcdram memristor stacked dram chip stack multi chip modules high bandwidth memory hbm developed by amd and hynix used in amd s fiji and nvidia s pascal references edit kada morihiro 2015 research and development history of three dimensional integration technology pdf three dimensional integration of semiconductors processing materials and applications springer pp 15 6 isbn 9783319186757 archived from the original pdf on 23 october 2021 retrieved 19 july 2019 a b micron reinvents dram memory linley group jag bolaria 12 september 2011 a b mearian lucas 25 september 2013 micron ships hybrid memory cube that boosts dram 15x computerworld com computerworld retrieved 4 november 2014 microsoft backs hybrid memory cube tech by gareth halfacree bit tech 9 may 2012 about us hybrid memory cube consortium archived from the original on 10 october 2011 retrieved 10 october 2011 faqs www micron com retrieved 5 december 2018 a b c hybrid memory cube hmc j thomas pawlowski micron hotchips 23 memory for exascale and micron s new memory component is called hmc hybrid memory cube archived 17 april 2012 at the wayback machine by dave resnick sandia national laboratories 2011 workshop on architectures i exascale and beyond 8 july 2011 micron s hybrid memory cubes win tech award by gareth halfacree bit tech 27 january 2012 best processor technology of 2011 the linley group tom halfhill 23 jan 2012 hybrid memory cube receives its finished spec promises up to 320gb per second by jon fingas engadget 3 april 2013 hmc 1 0 specification chapter 1 hmc architecture hmc 1 0 specification chapter 5 chaining hmc 1 0 specification chapter 19 packages for hmc 15g sr devices hybrid memory cube specification 1 0 pdf hmc consortium 1 january 2013 archived from the original pdf on 13 may 2013 retrieved 10 august 2016 hruska joel 25 september 2013 hybrid memory cube 160gb sec ram starts shipping is this the technology that finally kills ddr ram extremetech extreme tech retrieved 27 september 2013 hybrid memory cube consortium advances hybrid memory cube performance and industry adoption with release of new specification archived 1 august 2016 at the wayback machine 18 november 2014 hybrid memory cube specification 2 1 pdf hmc consortium 5 november 2015 archived from the original pdf on 9 january 2016 retrieved 10 august 2016 halfhill tom r 22 september 2014 sparc64 xifx uses memory cubes microprocessor report goering richard 6 august 2013 wide i o 2 hybrid memory cube hmc memory models advance 3d ic standards cadence com cadence design systems retrieved 8 december 2014 micron announces shift in high performance memory roadmap strategy external links edit official website of the hybrid memory cube consortium hmc 1 0 specification hmc 2 0 specification download form archived 17 june 2019 at the wayback machine revolutionary advancements in memory performance on youtube hybrid memory cube hmc archived 23 april 2014 at the wayback machine j thomas pawlowski micron hotchips 23 2011 stacking stairs against the memory wall archived 1 august 2016 at the wayback machine by nicole hemsoth hpc wire 2 april 2013 retrieved from https en wikipedia org w index php title hybrid_memory_cube oldid 1137726644 category computer memory hidden categories webarchive template wayback links use dmy dates from june 2014 official website different in wikidata and wikipedia this page was last edited on 6 february 2023 at 04 01 utc text is available under the creative commons attribution sharealike license 3 0 additional terms may apply by using this site you agree to the terms of use and privacy policy wikipedia is a registered trademark of the wikimedia foundation inc a non profit organization privacy policy about wikipedia disclaimers contact wikipedia mobile view developers statistics cookie statement