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quad data rate sram wikipedia 49 captures 11 may 2008 27 sep 2026 sep oct nov 29 2021 2022 2023 success fail about this capture timestamps the wayback machine http web archive org web 20221029204726 https en wikipedia org wiki quad_data_rate_sram quad data rate sram from wikipedia the free encyclopedia jump to navigation jump to search quad data rate qdr sram is a type of static ram computer memory that can transfer up to four words of data in each clock cycle like double data rate ddr sdram qdr sram transfers data on both rising and falling edges of the clock signal the main purpose of this capability is to enable reads and writes to occur at high clock frequencies without the loss of bandwidth due to bus turnaround cycles incurred in ddr sram qdr sram uses two clocks one for read data and one for write data and has separate read and write data buses also known as separate i o whereas ddr sram uses a single clock and has a single common data bus used for both reads and writes also known as common i o this helps to eliminate problems caused by the propagation delay of the clock wiring and allows the illusion of concurrent reads and writes as seen on the bus although internally the memory still has a conventional single port operations are pipelined but sequential when all data i o signals are accounted qdr sram is not 2x faster than ddr sram but is 100 efficient when reads and writes are interleaved in contrast ddr sram is most efficient when only one request type is continually repeated e g only read cycles when write cycles are interleaved with read cycles one or more cycles are lost for bus turnaround to avoid data contention which reduces bus efficiency most sram manufacturers constructed qdr and ddr sram using the same physical silicon differentiated by a post manufacturing selection e g blowing a fuse on chip citation needed qdr sram was designed for high speed communications and networking applications where data throughput is more important than cost power efficiency or density the technology was created by micron and cypress later followed by idt then nec samsung and renesas quad data rate ii memory is currently being designed by cypress semiconductor for radiation hardened environments contents 1 i o 1 1 clock inputs 1 2 control inputs 1 3 buses 2 clocking scheme 3 external links i o edit clock inputs edit 4 clock lines input clock k not k or k output clock c not c or c control inputs edit two control lines not write enable wps not read enable rps buses edit one address bus and two data buses address bus data in bus data out bus clocking scheme edit addresses read address latched on rising edge of c write address latched on rising edge of k in burst of 4 mode burst of 2 uses rising edge of not k data write if wps is low a data word on data in is latched on rising edge of k the next data word on data in is latched on rising edge of k read a read is a two cycle process if rps is low the first rising edge of c latches the read address a the second rising edge of c puts the data word from address a on the data out bus the next rising edge of c puts the next data word from address a 1 on the data out bus external links edit an4065 qdr ii qdr ii ddr ii ddr ii design guide retrieved from https en wikipedia org w index php title quad_data_rate_sram oldid 1087724095 categories computer memory hidden categories all articles with unsourced statements articles with unsourced statements from june 2021 navigation menu personal tools not logged in talk contributions create account log in namespaces article talk english views read edit view history more search navigation main page contents current events random article about wikipedia contact us donate contribute help learn to edit community portal recent changes upload file tools what links here related changes upload file special pages permanent link page information cite this page wikidata item print export download as pdf printable version languages suomi edit links this page was last edited on 14 may 2022 at 04 15 utc text is available under the creative commons attribution sharealike license 3 0 additional terms may apply by using this site you agree to the terms of use and privacy policy wikipedia is a registered trademark of the wikimedia foundation inc a non profit organization privacy policy about wikipedia disclaimers contact wikipedia mobile view developers statistics cookie statement