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the (347), gate (106), and (97), #silicon (64), was (46), with (43), process (37), source (33), drain (33), that (33), self (31), #aligned (28), mos (27), transistors (26), this (25), using (22), oxide (21), technology (20), transistor (19), mask (19), aluminum (19), for (18), are (18), edit (17), first (17), wafer (16), voltage (15), 1966 (14), 1968 (14), semiconductor (14), bower (14), not (13), faggin (13), field (13), integrated (13), gates (13), devices (13), steps (13), threshold (13), then (12), klein (11), photoresist (11), used (11), fairchild (11), had (11), use (10), circuits (10), ion (10), fabrication (10), regions (10), doping (10), layer (10), parasitic (10), history (9), from (9), effect (9), implantation (9), 1969 (9), chip (9), polysilicon (9), made (9), would (9), wikipedia (8), electron (8), isbn (8), october (8), low (8), high (8), also (8), exposed (8), which (8), top (8), where (8), type (8), amorphous (8), material (8), under (7), ieee (7), international (7), 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t insulators known making it possible to create new device types not feasible with conventional technology or with self aligned gates made with other materials particularly important are charge coupled devices ccd used for image sensors and non volatile memory devices using floating silicon gate structures these devices dramatically enlarged the range of functionality that could be achieved with solid state electronics certain innovations were required in order to make self aligned gates 3 a new process that would create the gates a switch from amorphous silicon to polycrystalline silicon because amorphous silicon would break where it passed over steps in the oxide insulating surface a photolithography method for etching polycrystalline silicon a method to reduce the impurities present in silicon prior to these innovations self aligned gates had been demonstrated on metal gate devices but their real impact was on silicon gate devices history edit the first mosfet was invented by mohamed atalla and dawon kahng at bell labs in 1959 4 5 they used silicon as channel material and a non self aligned aluminum al gate 6 the aluminum gate mos process technology started with the definition and doping of the source and drain regions of mos transistors followed by the gate mask that defined the thin oxide region of the transistors with additional processing steps an aluminum gate would then be formed over the thin oxide region completing the device fabrication due to the inevitable misalignment of the gate mask with respect to the source and drain mask it was necessary to have a fairly large overlap area between the gate region and the source and drain regions to ensure that the thin oxide region would bridge the source and drain even under worst case misalignment this requirement resulted in gate to source and gate to drain parasitic capacitances that were large and variable from wafer to wafer depending on the misalignment of the gate oxide mask with respect with the source and drain mask the result was an undesirable spread in the speed of the integrated circuits produced and a much lower speed than theoretically possible if the parasitic capacitances could be reduced to a minimum the overlap capacitance with the most adverse consequences on performance was the gate to drain parasitic capacitance cgd which by the well known miller effect augmented the gate to source capacitance of the transistor by cgd multiplied by the gain of the circuit to which that transistor was a part the impact was a considerable reduction in the switching speed of transistors in 1966 robert w bower realized that if the gate electrode was defined first it would be possible not only to minimize the parasitic capacitances between gate and source and drain but it would also make them insensitive to misalignment he proposed a method in which the aluminum gate electrode itself was used as a mask to define the source and drain regions of the transistor however since aluminum could not withstand the high temperature required for the conventional doping of the source and drain junctions bower proposed to use ion implantation a new doping technique still in development at hughes aircraft his employer and not yet available at other labs while bower s idea was conceptually sound in practice it did not work because it was impossible to adequately passivate the transistors and repair the radiation damage done to the silicon crystal structure by the ion implantation since these two operations would have required temperatures in excess of the ones survivable by the aluminum gate thus his invention provided a proof of principle but no commercial integrated circuit was ever produced with bower s method a more refractory gate material was needed in 1967 john c sarace and collaborators at bell labs replaced the aluminum gate with an electrode made of vacuum evaporated amorphous silicon and succeeded in building working self aligned gate mos transistors however the process as described was only a proof of principle suitable only for the fabrication of discrete transistors and not for integrated circuits and was not pursued any further by its investigators in 1968 the mos industry was prevalently using aluminum gate transistors with high threshold voltage hvt and desired to have a low threshold voltage lvt mos process in order to increase the speed and reduce the power dissipation of mos integrated circuits low threshold voltage transistors with aluminum gate demanded the use of 100 silicon orientation which however produced too low a threshold voltage for the parasitic mos transistors the mos transistors created when aluminum over the field oxide would bridge two junctions to increase the parasitic threshold voltage beyond the supply voltage it was necessary to increase the n type doping level in selected regions under the field oxide and this was initially accomplished with the use of a so called channel stopper mask and later with ion implantation development of the silicon gate technology at fairchild edit the sgt was the first process technology used to fabricate commercial mos integrated circuits that was later widely adopted by the entire industry in the 1960s in late 1967 tom klein working at the fairchild semiconductor r d labs and reporting to les vadasz realized that the work function difference between heavily p type doped silicon and n type silicon was 1 1 volt lower than the work function difference between aluminum and the same n type silicon this meant that the threshold voltage of mos transistors with silicon gate could be 1 1 volt lower than the threshold voltage of mos transistors with aluminum gate fabricated on the same starting material therefore one could use starting material with 111 silicon orientation and simultaneously achieve both an adequate parasitic threshold voltage and low threshold voltage transistors without the use of a channel stopper mask or ion implantation under the field oxide with p type doped silicon gate it would therefore be possible not only to create self aligned gate transistors but also a low threshold voltage process by using the same silicon orientation of the high threshold voltage process in february 1968 federico faggin joined les vadasz s group and was put in charge of the development of a low threshold voltage self aligned gate mos process technology faggin s first task was to develop the precision etching solution for the amorphous silicon gate and then he created the process architecture and the detailed processing steps to fabricate mos ics with silicon gate he also invented the buried contacts a method to make direct contact between amorphous silicon and silicon junctions without the use of metal a technique that allowed a much higher circuit density particularly for random logic circuits after validating and characterizing the process using a test pattern he designed faggin made the first working mos silicon gate transistors and test structures by april 1968 he then designed the first integrated circuit using silicon gate the fairchild 3708 an 8 bit analog multiplexer with decoding logic that had the same functionality of the fairchild 3705 a metal gate production ic that fairchild semiconductor had difficulty making on account of its rather stringent specifications the availability of the 3708 in july 1968 provided also a platform to further improve the process during the following months leading to the shipment of the first 3708 samples to customers in october 1968 and making it commercially available to the general market before the end of 1968 during the period july to october 1968 faggin added two additional critical steps to the process replacing the vacuum evaporated amorphous silicon with poly crystalline silicon obtained by vapor phase deposition this step became necessary since evaporated amorphous silicon did break where it passed over steps in the surface of the oxide the use of phosphorus gettering to soak up the impurities always present in the transistor causing reliability problems phosphorus gettering allowed to considerably reduce the leakage current and to avoid the threshold voltage drift that still plagued mos technology with aluminum gate mos transistors with aluminum gate were not suitable for phosphorus gettering due to the high temperature required with silicon gate the long term reliability of mos transistors soon reached the level of bipolar ics removing one major obstacle to the wide adoption of mos technology by the end of 1968 the silicon gate technology had achieved impressive results although the 3708 was designed to have approximately the same area as the 3705 to facilitate using the same production tooling as the 3705 it could have been made considerably smaller nonetheless it had superior performance compared with the 3705 it was 5 times faster it had about 100 times less leakage current and the on resistance of the large transistors making up the analog switches was 3 times lower 7 pp6 7 commercialization at intel edit the silicon gate technology sgt was adopted by intel upon its founding july 1968 and within a few years became the core technology for the fabrication of mos integrated circuits worldwide lasting to this day intel was also the first company to develop non volatile memory using floating silicon gate transistors the first memory chip to use silicon gate technology was the intel 1101 sram static random access memory chip fabricated in 1968 and demonstrated in 1969 8 the first commercial single chip microprocessor the intel 4004 was developed by faggin using his silicon gate mos ic technology marcian hoff stan mazor and masatoshi shima contributed to the architecture 9 original documents on sgt edit bower rw and dill rg 1966 insulated gate field effect transistors fabricated using the gate as source drain mask ieee international electron devices meeting 1966 faggin f klein t and vadasz l insulated gate field effect transistor integrated circuits with silicon gates ieee international electron devices meeting washington d c 1968 1 us 3475234 kerwin robert e klein donald l sarace john c method for making mis structures published 28 10 1969 assigned to bell telephone laboratories inc federico faggin and thomas klein a faster generation of mos devices with low thresholds is riding the crest of the new wave silicon gate ic s cover story on fairchild 3708 electronics magazine september 29 1969 vadasz l l grove a s rowe t a moore g e october 1969 silicon gate technology ieee spectrum pp 27 35 f faggin t klein silicon gate technology solid state electronics 1970 vol 13 pp 1125 1144 us 3673471 klein thomas faggin federico doped semiconductor electrodes for mos type devices published 1972 06 27 assigned to fairchild camera and instrument corporation patents edit the self aligned gate design was patented in 1969 by the team of kerwin klein and sarace 10 it was independently invented by robert w bower u s 3 472 712 issued october 14 1969 filed october 27 1966 the bell labs kerwin et al patent was not filed until march 27 1967 several months after r w bower and h d dill had published and presented the first publication of this work at the international electron device meeting washington d c in 1966 11 in a legal action involving bower the third circuit court of appeals determined that kerwin klein and sarace were the inventors of the self aligned silicon gate transistor on that basis they were awarded the basic patent us 3 475 234 actually the self aligned gate mosfet was invented by robert w bower u s 3 472 712 issued october 14 1969 filed october 27 1966 the bell labs kerwin et al patent 3 475 234 was not filed until march 27 1967 several months after the r w bower and h d dill published and presented the first publication of this work entitled insulated gate field effect transistors fabricated using the gate as source drain mask at the international electron device meeting washington d c 1966 bower s work described the self aligned gate mosfet made with both aluminum and polysilicon gates it used both ion implantation and diffusion to form the source and drain using the gate electrode as the mask to define the source and drain regions the bell labs team attended this meeting of the iedm in 1966 and they discussed this work with bower after his presentation in 1966 bower had first made the self aligned gate using aluminum as the gate and before presentation in 1966 made the device using polysilicon as the gate the self aligned gate typically involves ion implantation another semiconductor process innovation of the 1960s the histories of ion implantation and self aligned gates are highly interrelated as recounted in an in depth history by r b fair 12 the first commercial product using self aligned silicon gate technology was the fairchild 3708 8 bit analog multiplexor in 1968 designed by federico faggin who pioneered several inventions in order to turn the aforementioned non working proofs of concept into what the industry actually adopted thereafter 13 14 manufacturing process edit the importance of self aligned gates comes in the process used to make them the process of using the gate oxide as a mask for the source and drain diffusion both simplifies the process and greatly improves the yield process steps edit the following are the steps in creating a self aligned gate 15 a cleanroom facility where these steps are performed these steps were first created by federico faggin and used in the silicon gate technology process developed at fairchild semiconductor in 1968 for the fabrication of the first commercial integrated circuit using it the fairchild 3708 16 1 wells on the field oxide are etched where the transistors are to be formed each well defines the source drain and active gate regions of an mos transistor 2 using a dry thermal oxidation process a thin layer 5 200 nm of gate oxide sio 2 is grown on the silicon wafer 3 using a chemical vapor deposition cvd process a layer of polysilicon is grown on top of the gate oxide 4 a layer of photoresist is applied on top of the polysilicon 5 a mask is placed on top of the photoresist and exposed to uv light this breaks down the photoresist layer in areas where the mask didn t protect it 6 photoresist is exposed with a specialized developer solution this is intended to remove the photoresist that was broken down by the uv light 7 the polysilicon and gate oxide that is not covered by photoresist is etched away with a buffered ion etch process this is usually an acid solution containing hydrofluoric acid 8 the rest of the photoresist is stripped from the silicon wafer there is now a wafer with polysilicon over the gate oxide and over the field oxide 9 the thin oxide is etched away exposing the source and drain regions of the transistor except in the gate region which is protected by the polysilicon gate 10 using a conventional doping process or a process called ion implantation the source drain and the polysilicon are doped the...