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Text of the page (random words):
e origin 2000 was succeeded by the origin 3000 in july 2000 and was discontinued on june 30 2002 the origin 2000 known as asci blue mountain at the los alamos national laboratory in 2001 contents 1 models 2 hardware 2 1 architecture 2 1 1 router boards 2 1 1 1 null router 2 1 1 2 star router 2 1 1 3 standard router rack router 2 1 1 4 meta router cray router 2 2 nodes 2 2 1 processor 2 2 2 main memory and directory memory 2 2 3 hub asic 2 3 i o subsystem 3 notes 4 sgi timeline 5 references models edit the family was announced on october 7 1996 1 the project was code named lego and also known as sn0 to indicate the first in a series of scalable node architectures contrasting with previous symmetric multiprocessor architectures in the sgi challenge series 2 model of cpus memory i o chassis introduced discontinued origin 2100 2 to 8 up to 16 gb 12 xio deskside may 31 2002 origin 2200 2 to 8 up to 16 gb 12 xio deskside may 31 2002 origin 2400 8 to 32 up to 64 gb 96 xio 1 to 4 racks may 31 2002 origin 2800 32 to 128 256 and 512 unsupported up to 256 gb 512 gb unsupported 384 xio 1 to 9 racks with meta router may 31 2002 the origin 2100 is mostly the same as the other models except that it is not upgradeable to other models unless the router cards etc were replaced the highest cpu count that sgi marketed for the origin 2000 is 128 cpus above 64 cpus the product was originally branded cray origin 2000 since cray research has just been merged with sgi 1 three origin 2000 models are capable of using 512 cpus and 512 gb of memory but these were never marketed as a system to customers one of the 512 cpu origin 2000 series was installed at sgi s facility in eagan minnesota for test purposes and the other two were sold to nasa ames research center in mountain view california for specialized scientific computing the 512 cpu origin 2800s cost roughly 40 million each and the delivery of the origin 3000 systems scalable up to 512 or 1024 cpus at a lower price per performance made the 512 cpu origin 2800 obsolete several customers also bought 256 cpu origin 2000 series systems although they were never marketed as a product by sgi either the largest installation of sgi origin 2000 series was accelerated strategic computing initiative asci blue mountain at los alamos national labs it included 48 origin 2000 series 128 cpu systems all connected via high performance parallel interface hippi for a total of 6144 processors at the time it was tested it placed second on the top500 list of fastest computers in the world that test was completed with only 40 nodes of 128 cpus each and recorded a sustained 1 6 teraflops with all nodes connected it was able to sustain 2 1 teraflops and peak of over 2 5 teraflops los alamos national laboratory also had another 12 origin 128 cpu system for a total of 1536 cpus as part of the same testing the climate simulation laboratory at the national center for atmospheric research ncar had an origin 2000 system named ute with 128 cpus it was delivered on may 18 1998 and decommissioned on july 15 2002 3 a smaller system at ncar was named dataproc delivered on march 29 with 16 cpus 4 the systems at nasa ames included the one named for harvard lomax with 512 cpus one named for joseph steger with 128 cpus one named for grace hopper with 64cpus and one named for alan turing with 24 cpus 5 6 hardware edit each origin 2000 module is based on nodes that are plugged into a backplane each module can contain up to four node boards two router boards and twelve xio options the modules are then mounted inside a deskside enclosure or a rack deskside enclosures can only contain one module while racks can contain two in configurations with more than two modules multiple racks are used enclosure width height depth weight 1 deskside 53 cm 21 inches 65 cm 25 5 inches 58 cm 23 inches 98 kg 215 lb rack 71 cm 28 inches 185 cm 73 inches 102 cm 40 inches 317 kg 700 lb 1 figures specified are for maximum configurations the origin 200 uses some of the architectural components but in a very different physical realization that is not scalable 7 architecture edit an origin 2000 system is composed of nodes linked together by an interconnection network it uses the distributed shared memory sometimes called scalable shared memory multiprocessing s 2 mp architecture the origin 2000 uses numalink originally named craylink for its system interconnect the nodes are connected to router boards which use numalink cables to connect to other nodes through their routers the origin 2000 s network topology is a bristled fat hypercube in configurations with more than 64 processors a hierarchical fat hypercube network topology is used instead additional numalink cables called xpress links can be installed between unused standard router ports to reduce latency and increase bandwidth xpress links can only be used in systems that have 16 or 32 processors as these are the only configurations with a network topology that enables unused ports to be used in such a way the architecture has its roots in the dash project at stanford university led by john l hennessy which included two of the origin designers 8 9 router boards edit there are four different router boards used by the origin 2000 each successive router board allows a larger amount of nodes to be connected null router edit the null router connects two nodes in the same module a system using the null router cannot be expanded as there are no external connectors star router edit the star router can connect up to four nodes it is always used in conjunction with a standard router to function correctly standard router rack router edit the standard router can connect up to 32 nodes it contains an application specific integrated circuit asic known as the scalable pipelined interconnect for distributed endpoint routing spider which serves as a router for the numalink network the spider asic has six ports each with a pair of unidirectional links connected to a crossbar which enables the ports to communicate with one another 10 meta router cray router edit the meta router is used in conjunction with standard routers to connect more than 32 nodes it can connect up to 64 nodes nodes edit each origin 2000 node fits on a single 16 by 11 printed circuit board that contains one or two processors the main memory the directory memory and the hub asic the node board plugs into the backplane through a 300 pad cpop compression pad on pad connector the connector actually combines two connections one to the numalink router network and another to the xio i o subsystem processor edit each processor and their secondary cache is contained on a himm horizontal inline memory module daughter card that plugs into the node board at the time of introduction the origin 2000 used the ip27 board featuring one or two r10000 processors clocked at 180 mhz with 1 mb secondary cache s a high end model with two 195 mhz r10000 processors with 4 mb secondary caches was also available in february 1998 the ip31 board was introduced with two 250 mhz r10000 processors with 4 mb secondary caches later the ip31 board was upgraded to support two 300 350 or 400 mhz r12000 processors the 300 and 400 mhz models had 8 mb l2 caches while the 350 mhz model had 4 mb l2 caches near the end of its life a variant of the ip31 board that could utilize the 500 mhz r14000 with 8 mb l2 caches was made available main memory and directory memory edit each node board can support a maximum of 4 gb of memory through 16 dimm slots by using proprietary ecc memory sdram dimms with capacities of 16 32 64 and 256 mb because the memory bus is 144 bits wide 128 bits for data and 16 bits for ecc memory modules are inserted in pairs to support the origin 2000 distributed shared memory model the memory modules are proprietary and include directory memory which contains information on the contents of remote caches for maintaining cache coherency supporting up to 32 processors additional directory memory is required in configurations with more than 32 processors the additional directory memory is contained on proprietary dimms that are inserted into eight dimm slots set aside for its use hub asic edit the hub asic interfaces the processors memory and xio to the numalink 2 system interconnect the asic contains five major sections the crossbar referred to as the xb the i o interface referred to as the ii the network interface referred to as the ni the processor interface referred to as the pi and the memory and directory interface referred to as the dm which also serves as the memory controller the interfaces communicate with each other via fifo buffers that are connected to the crossbar when two processors are connected to the hub asic the node does not behave in a smp fashion instead the two processors operate separately and their buses are multiplexed over the single processor interface this was done to save pins on the hub asic the hub asic is clocked at 100 mhz and contains 900 000 gates fabricated in a five layer metal process i o subsystem edit the i o subsystem is based around the crossbow xbow asic which shares many similarities with the spider asic since the xbow asic is intended for use with the simpler xio protocol its hardware is also simpler allowing the asic to feature eight ports compared with the spider asic s six ports two of the ports connect to the node boards and the remaining six to xio cards while the i o subsystem s native bus is xio pci x and vme64 buses can also be used provided by xio bridges an io6 base i o board is present in every system it is a xio card that provides 1 10 100base tx port 2 serial ports provided by dual uarts 1 internal fast 20 ultrascsi single ended port 1 external wide ultrascsi singled ended port 1 real time interrupt output for frame sync 1 real time interrupt input edge triggered flash prom nvram and real time clock the io6g g for graphics had 2 additional serial ports and keyboard mouse ports plus the above ports the io6g was required on systems with the onyx graphics pipes cards to connect keyboard mouse notes edit a b silicon graphics and cray research unveil modular origin server family high bandwidth systems revolutionize computer buying economics with seamless scalability press release october 7 1996 archived from the original on july 7 1997 retrieved september 21 2013 silicon graphics completely renews its stations servers computer business review october 7 1996 sgi origin 2000 ute 1998 2002 scd supercomputer gallery national center for atmospheric research retrieved september 21 2013 sgi origin 2000 dataproc 1999 2004 scd supercomputer gallery national center for atmospheric research retrieved september 21 2013 nasa to name supercomputer after columbia astronaut press release nasa may 10 2004 retrieved september 21 2013 raymond d turney october 22 2004 comparison of 250 mhz r10k origin 2000 and 400 mhz origin 2000 using nas parallel benchmarks pdf nas technical report 01 007 retrieved september 21 2013 james laudon and daniel lenoski february 23 1997 system overview of the sgi origin 200 2000 product line proceedings ieee compcon 97 digest of papers proceedings of the 42nd ieee international computer conference ieee pp 150 156 doi 10 1109 cmpcon 1997 584688 isbn 978 0 8186 7804 2 s2cid 16688054 cite book cs1 maint uses authors parameter link daniel lenoski james laudon truman joe david nakahira luis stevens anoop gupta and john l hennessy may 1992 the dash prototype implementation and performance proceedings of the 19th annual international symposium on computer 2 2 92 103 doi 10 1145 146628 139706 cite journal cs1 maint uses authors parameter link james laudon and daniel lenoski may 1997 the sgi origin a ccnuma highly scalable server pdf proceedings of the 24th annual international symposium on computer architecture 25 2 241 251 doi 10 1145 384286 264206 cite journal cs1 maint uses authors parameter link mike galles 1996 scalable pipelined interconnect for distributed endpoint routing the sgi spider chip proceedings of hot interconnects symposium stanford university 141 146 sgi timeline edit references edit wikimedia commons has media related to silicon graphics origin 2000 ásgeir th eiríksson john keen alex silbey swami venkataraman michael woodacre 1997 origin system design methodology and experience 1m gate asics and beyond proceedings of the 42nd ieee international computer conference ieee pp 157 164 doi 10 1109 cmpcon 1997 584690 origin 2000 rackmount owner s guide 007 3456 003 june 15 1998 silicon graphics origin and onyx2 theory of operations manual 007 3439 002 june 15 1998 silicon graphics preceded by challenge sgi origin 2000 1996 2003 succeeded by origin 3000 preceded by onyx sgi onyx 2 1996 2003 succeeded by onyx 3000 v t e silicon graphics company silicon graphics 1981 2009 silicon graphics international 2009 2016 people kurt akeley rick belluzzo david j brown james h clark paul haeberli herb kuta abbey silverstone computer architectures motorola 68000 sgi iris former models mips iris 4d indigo indigo² and challenge m indy crimson o2 octane challenge onyx origin 200 origin 2000 onyx2 origin and onyx 3000 fuel tezro ia 32 itanium x86 64 visual workstation altix prism virtu graphics hardware geometry engine elan extreme impact vpro realityengine infinitereality irisvision reality coprocessor monitors 1600sw other technology irix image format mex workspace 4sight interactive desktop xsgi 4dwm xfs iris gl opengl openldi gio xio numalink nintendo 64 retrieved from https en wikipedia org w index php title sgi_origin_2000 oldid 1106892768 categories sgi servers hidden categories cs1 maint uses authors parameter pages using the easytimeline extension use mdy dates from october 2019 wikipedia introduction cleanup from october 2019 all pages needing cleanup articles covered by wikiproject wikify from october 2019 all articles covered by wikiproject wikify articles with short description short description is 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