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128 bit computing wikipedia 184 captures 17 apr 2020 23 sep 2026 sep oct nov 16 2021 2022 2023 success fail about this capture timestamps the wayback machine http web archive org web 20221016140407 https en wikipedia org wiki 128 bit_computing 128 bit computing from wikipedia the free encyclopedia jump to navigation jump to search computer architecture bit width computer architecture bit widths bit 1 2 4 8 12 16 18 20 24 26 28 30 31 32 36 40 45 48 60 64 128 256 512 bit slicing application 8 16 32 64 binary floating point precision 16 ½ 24 32 1 40 64 2 80 128 4 256 8 decimal floating point precision 32 64 128 v t e in computer architecture 128 bit integers memory addresses or other data units are those that are 128 bits 16 octets wide also 128 bit central processing unit cpu and arithmetic logic unit alu architectures are those that are based on registers address buses or data buses of that size while there are currently no mainstream general purpose processors built to operate on 128 bit integers or addresses a number of processors do have specialized ways to operate on 128 bit chunks of data contents 1 representation 2 history 3 hardware 4 software 4 1 uses 5 references representation edit 128 bit processors could be used for addressing directly up to 2 128 over 3 40 10 38 bytes which would greatly exceed the total data captured created or replicated on earth as of 2018 which has been estimated to be around 33 zettabytes over 2 74 bytes 1 a 128 bit register can store 2 128 over 3 40 10 38 different values the range of integer values that can be stored in 128 bits depends on the integer representation used with the two most common representations the range is 0 through 340 282 366 920 938 463 463 374 607 431 768 211 455 2 128 1 for representation as an unsigned binary number and 170 141 183 460 469 231 731 687 303 715 884 105 728 2 127 through 170 141 183 460 469 231 731 687 303 715 884 105 727 2 127 1 for representation as two s complement quadruple precision 128 bit floating point numbers can store 113 bit fixed point numbers or integers accurately without losing precision thus 64 bit integers in particular quadruple precision floats can also represent any position in the observable universe with at least micrometer precision citation needed decimal128 floating point numbers can represent numbers with up to 34 significant digits history edit a 128 bit multicomparator was described by researchers in 1976 2 the ibm system 360 model 85 3 and ibm system 370 and its successors support 128 bit floating point arithmetic the siemens 7 700 and 7 500 series mainframes and their successors support 128 bit floating point arithmetic 4 most modern cpus feature single instruction multiple data simd instruction sets streaming simd extensions altivec etc where 128 bit vector registers are used to store several smaller numbers such as four 32 bit floating point numbers a single instruction can then operate on all these values in parallel however these processors do not operate on individual numbers that are 128 binary digits in length only their vector registers have the size of 128 bits the dec vax supported operations on 128 bit integer o or octaword and 128 bit floating point h float or hfloat datatypes support for such operations was an upgrade option rather than being a standard feature since the vax s registers were 32 bits wide a 128 bit operation used four consecutive registers or four longwords in memory the icl 2900 series provided a 128 bit accumulator and its instruction set included 128 bit floating point and packed decimal arithmetic a cpu with 128 bit multimedia extensions was designed by researchers in 1999 5 the dreamcast and the playstation 2 among the sixth generation of video game consoles used the term 128 bit in their marketing to describe their capability the playstation 2 s cpu had 128 bit simd capabilities 6 7 neither console supported 128 bit addressing or 128 bit integer arithmetic modern graphics processing unit gpu chips may operate data across a 128 bit bus 8 hardware edit the risc v isa specification from 2016 includes a reservation for a 128 bit version of the architecture but the details remain undefined intentionally because there is yet so little practical experience with such large word size 9 software edit in the same way that compilers emulate e g 64 bit integer arithmetic on architectures with register sizes less than 64 bits some compilers also support 128 bit integer arithmetic for example the gcc c compiler 4 6 and later has a 128 bit integer type __int128 for some architectures 10 gcc and compatible compilers signal the presence of 128 bit arithmetic when the macro __sizeof_int128__ is defined 11 for the c programming language 128 bit support is optional e g via the int128_t type or it can be implemented by a compiler specific extension the rust programming language has built in support for 128 bit integers originally via llvm which is implemented on all platforms 12 a 128 bit type provided by a c compiler can be available in perl via the math int128 module 13 uses edit the free software used to implement risc v architecture is defined for 32 64 and 128 bits of integer data width universally unique identifiers uuid consist of a 128 bit value ipv6 routes computer network traffic amongst a 128 bit range of addresses zfs is a 128 bit file system 128 bits is a common key size for symmetric ciphers and a common block size for block ciphers in cryptography the ibm i virtual instruction set defines all pointers as 128 bit this gets translated to the hardware s real instruction set as required allowing the underlying hardware to change without needing to recompile the software past hardware was 48 bit cisc while current hardware is 64 bit powerpc because pointers are defined to be 128 bit future hardware may be 128 bit without software incompatibility increasing the word size can speed up multiple precision mathematical libraries with applications to cryptography and potentially speed up algorithms used in complex mathematical processing numerical analysis signal processing complex photo editing and audio and video processing md5 is a hash function producing a 128 bit hash value apache avro uses a 128 bit random number as synchronization marker for efficient splitting of data files 14 15 references edit reinsel david gantz john rydning john november 2018 the digitalization of the world from edge to core pdf seagate technology idc p 3 archived pdf from the original on 7 september 2021 retrieved 14 september 2021 mead carver a pashley richard d britton lee d daimon yoshiaki t sando stewart f jr october 1976 128 bit multicomparator pdf ieee journal of solid state circuits 11 5 692 695 bibcode 1976ijssc 11 692m doi 10 1109 jssc 1976 1050799 s2cid 27262034 archived pdf from the original on 3 november 2018 padegs a 1968 structural aspects of the system 360 model 85 iii extensions to floating point architecture ibm systems journal 7 22 29 doi 10 1147 sj 71 0022 assembler instructions bs2000 osd 1993 suzuoki m kutaragi k hiroi t magoshi h okamoto s oka m ohba a yamamoto y furuhashi m tanaka m yutaka t okada t nagamatsu m urakawa y funyu m kunimatsu a goto h hashimoto k ide n murakami h ohtaguro y aono a november 1999 a microprocessor with a 128 bit cpu ten floating point mac s four floating point dividers and an mpeg 2 decoder ieee journal of solid state circuits 34 11 1608 1618 bibcode 1999ijssc 34 1608s doi 10 1109 4 799870 john l hennessy and david a patterson computer architecture a quantitative approach third edition isbn 1 55860 724 2 keith diefendorff sony s emotionally charged chip microprocessor report volume 13 number 5 april 19 1999 microdesign resources woligroski don 24 july 2006 the graphics processor tom s hardware archived from the original on 11 april 2013 retrieved 24 february 2013 waterman andrew asanović krste the risc v instruction set manual volume i base user level isa version 2 2 university of california berkeley eecs 2016 118 retrieved 25 may 2017 gcc 4 6 release series changes new features and fixes retrieved 25 july 2016 marc glisse 26 august 2015 128 bit integer nonsensical documentation gcc help retrieved 23 january 2020 i128 rust doc rust lang org retrieved 25 june 2020 math int128 metacpan org retrieved 25 june 2020 kleppmann martin 24 january 2013 re synchronization markers archived from the original on 27 september 2015 apache avro 1 8 0 specification apache software foundation v t e processor technologies models abstract machine stored program computer finite state machine with datapath hierarchical deterministic finite automaton queue automaton cellular automaton quantum cellular automaton turing machine alternating turing machine universal post turing quantum nondeterministic turing machine probabilistic turing machine hypercomputation zeno machine belt machine stack machine register machines counter pointer random access random access stored program architecture microarchitecture von neumann harvard modified dataflow transport triggered cellular endianness memory access numa huma load store register memory cache hierarchy memory hierarchy virtual memory secondary storage heterogeneous fabric multiprocessing cognitive neuromorphic instruction set architectures types orthogonal instruction set cisc risc application specific edge trips vliw epic misc oisc nisc zisc visc architecture quantum computing comparison addressing modes instruction sets motorola 68000 series vax pdp 11 x86 arm stanford mips mips mips x power power powerpc power isa clipper architecture sparc superh dec alpha etrax cris m32r unicore itanium openrisc risc v microblaze lmc system 3x0 s 360 s 370 s 390 z architecture tilera isa visc architecture epiphany architecture others execution instruction pipelining pipeline stall operand forwarding classic risc pipeline hazards data dependency structural control false sharing out of order scoreboarding tomasulo algorithm reservation station re order buffer register renaming wide issue speculative branch prediction memory dependence prediction parallelism level bit bit serial word instruction pipelining scalar superscalar task thread process data vector memory distributed multithreading temporal simultaneous hyperthreading speculative preemptive cooperative flynn s taxonomy sisd simd array processing simt pipelined processing associative processing swar misd mimd spmd processor performance transistor count instructions per cycle ipc cycles per instruction cpi instructions per second ips floating point operations per second flops transactions per second tps synaptic updates per second sups performance per watt ppw cache performance metrics computer performance by orders of magnitude types central processing unit cpu graphics processing unit gpu gpgpu vector barrel stream tile processor coprocessor pal asic fpga fpoa cpld multi chip module mcm system in a package sip package on a package pop by application embedded system microprocessor microcontroller mobile notebook ultra low voltage asip soft microprocessor systems on chip system on a chip soc multiprocessor mpsoc programmable psoc network on a chip noc hardware accelerators coprocessor ai accelerator graphics processing unit gpu image processor vision processing unit vpu physics processing unit ppu digital signal processor dsp tensor processing unit tpu secure cryptoprocessor network processor baseband processor word size 1 bit 4 bit 8 bit 12 bit 15 bit 16 bit 24 bit 32 bit 48 bit 64 bit 128 bit 256 bit 512 bit bit slicing others variable core count single core multi core manycore heterogeneous architecture components core cache cpu cache scratchpad memory data cache instruction cache replacement policies coherence bus clock rate clock signal fifo functional units arithmetic logic unit alu address generation unit agu floating point unit fpu memory management unit mmu load store unit translation lookaside buffer tlb branch predictor branch target predictor integrated memory controller imc memory management unit instruction decoder logic combinational sequential glue logic gate quantum array registers processor register status register stack register register file memory buffer memory address register program counter control unit hardwired control unit instruction unit data buffer write buffer microcode rom horizontal microcode counter datapath multiplexer demultiplexer adder multiplier cpu binary decoder address decoder sum addressed decoder barrel shifter circuitry integrated circuit 3d mixed signal power management boolean digital analog quantum switch power management pmu apm acpi dynamic frequency scaling dynamic voltage scaling clock gating performance per watt ppw related history of general purpose cpus microprocessor chronology processor design digital electronics hardware security module semiconductor device fabrication tick tock model pin grid array chip carrier retrieved from https en wikipedia org w index php title 128 bit_computing oldid 1115428568 categories data unit hidden categories articles with short description short description matches wikidata use dmy dates from december 2019 all articles with unsourced statements articles with unsourced statements from may 2020 navigation menu personal tools not logged in talk contributions create account log in namespaces article talk english views read edit view history more search navigation main page contents current events random article about wikipedia contact us donate contribute help learn to edit community portal recent changes upload file tools what links here related changes upload file special pages permanent link page information cite this page wikidata item print export download as pdf printable version languages العربية español فارسی français 한국어 italiano bahasa melayu 日本語 norsk bokmål português română русский українська 中文 edit links this page was last edited on 11 october 2022 at 12 17 utc text is available under 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