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ttently run the agc when it was operating in the standby mode central registers edit the agc had four 16 bit registers for general computational use called the central registers a the accumulator for general computation z the program counter the address of the next instruction to be executed q the remainder from the dv instruction and the return address after tc instructions lp the lower product after mp instructions there were also four locations in core memory at addresses 20 23 dubbed editing locations because whatever was stored there would emerge shifted or rotated by one bit position except for one that shifted right seven bit positions to extract one of the seven bit interpretive op codes that were packed two to a word this was common to block i and block ii agcs other registers edit dsky and agc prototypes on display at the computer history museum the agc is opened up showing its logic modules prototype logic module from block i agc block ii logic module with flat pack ics the agc had additional registers that were used internally in the course of operation s 12 bit memory address register the lower portion of the memory address bank fbank 4 bit rom bank register to select the 1 kiloword rom bank when addressing in the fixed switchable mode ebank 3 bit ram bank register to select the 256 word ram bank when addressing in the erasable switchable mode sbank super bank 1 bit extension to fbank required because the last 4 kilowords of the 36 kiloword rom was not reachable using fbank alone sq 4 bit sequence register the current instruction g 16 bit memory buffer register to hold data words moving to and from memory x the x input to the adder the adder was used to perform all 1 s complement arithmetic or the increment to the program counter z register y the other y input to the adder u not really a register but the output of the adder the one s complement sum of the contents of registers x and y b general purpose buffer register also used to pre fetch the next instruction at the start of the next instruction the upper bits of b containing the next op code were copied to sq and the lower bits the address were copied to s c not a separate register but the one s complement of the b register in four 16 bit input registers out five 16 bit output registers instruction set edit the instruction format used 3 bits for opcode and 12 bits for address block i had 11 instructions tc ccs index xch cs ts ad and mask basic and su mp and dv extra the first eight called basic instructions were directly accessed by the 3 bit op code the final three were denoted as extracode instructions because they were accessed by performing a special type of tc instruction called extend immediately before the instruction the block i agc instructions consisted of the following tc transfer control an unconditional branch to the address specified by the instruction the return address was automatically stored in the q register so the tc instruction could be used for subroutine calls ccs count compare and skip a complex conditional branch instruction the a register was loaded with data retrieved from the address specified by the instruction because the agc uses ones complement notation there are two representations of zero when all bits are set to zero this is called plus zero if all bits are set to one this is called minus zero the diminished absolute value dabs of the data was then computed and stored in the a register if the number was greater than zero the dabs decrements the value by 1 if the number was negative it is complemented before the decrement is applied this is the absolute value diminished means decremented but not below zero therefore when the agc performs the dabs function positive numbers will head toward plus zero and so will negative numbers but first revealing their negativity via the four way skip below the final step in ccs is a four way skip depending upon the data in register a before the dabs if register a was greater than 0 ccs skips to the first instruction immediately after ccs if register a contained plus zero ccs skips to the second instruction after ccs less than zero causes a skip to the third instruction after ccs and minus zero skips to the fourth instruction after ccs the primary purpose of the count was to allow an ordinary loop controlled by a positive counter to end in a ccs and a tc to the beginning of the loop equivalent to an ibm 360 s bct the absolute value function was deemed important enough to be built into this instruction when used for only this purpose the sequence after the ccs was tc 2 tc 2 ad one a curious side effect was the creation and use of ccs holes when the value being tested was known to be never positive which occurred more often than one might suppose that left two whole words unoccupied and a special committee was responsible for assigning data constants to these holes index add the data retrieved at the address specified by the instruction to the next instruction index can be used to add or subtract an index value to the base address specified by the operand of the instruction that follows index this method is used to implement arrays and table look ups since the addition was done on both whole words it was also used to modify the op code in a following extracode instruction and on rare occasions both functions at once resume a special instance of index index 25 this is the instruction used to return from interrupts it causes execution to resume at the interrupted location xch exchange exchange the contents of memory with the contents of the a register if the specified memory address is in fixed read only memory the memory contents are not affected and this instruction simply loads register a if it is in erasable memory overflow correction is achieved by storing the leftmost of the 16 bits in a as the sign bit in memory but there is no exceptional behavior like that of ts cs clear and subtract load register a with the one s complement of the data referenced by the specified memory address ts transfer to storage store register a at the specified memory address ts also detects and corrects for overflows in such a way as to propagate a carry for multi precision add subtract if the result has no overflow leftmost 2 bits of a the same nothing special happens if there is overflow those 2 bits differ the leftmost one goes the memory as the sign bit register a is changed to 1 or 1 accordingly and control skips to the second instruction following the ts whenever overflow is a possible but abnormal event the ts was followed by a tc to the no overflow logic when it is a normal possibility as in multi precision add subtract the ts is followed by caf zero caf xch to fixed memory to complete the formation of the carry 1 0 or 1 into the next higher precision word angles were kept in single precision distances and velocities in double precision and elapsed time in triple precision ad add add the contents of memory to register a and store the result in a the 2 leftmost bits of a may be different overflow state before and or after the ad the fact that overflow is a state rather than an event forgives limited extents of overflow when adding more than two numbers as long as none of the intermediate totals exceed twice the capacity of a word mask perform a bit wise boolean and of memory with register a and store the result in register a mp multiply multiply the contents of register a by the data at the referenced memory address and store the high order product in register a and the low order product in register lp the parts of the product agree in sign dv divide divide the contents of register a by the data at the referenced memory address store the quotient in register a and the absolute value of the remainder in register q unlike modern machines fixed point numbers were treated as fractions notional decimal point just to right of the sign bit so you could produce garbage if the divisor was not larger than the dividend there was no protection against that situation in the block ii agc a double precision dividend started in a and l the block ii lp and the correctly signed remainder was delivered in l that considerably simplified the subroutine for double precision division su subtract subtract one s complement the data at the referenced memory address from the contents of register a and store the result in a instructions were implemented in groups of 12 steps called timing pulses the timing pulses were named tp1 through tp12 each set of 12 timing pulses was called an instruction subsequence simple instructions such as tc executed in a single subsequence of 12 pulses more complex instructions required several subsequences the multiply instruction mp used 8 subsequences an initial one called mp0 followed by an mp1 subsequence which was repeated 6 times and then terminated by an mp3 subsequence this was reduced to 3 subsequences in block ii each timing pulse in a subsequence could trigger up to 5 control pulses the control pulses were the signals which did the actual work of the instruction such as reading the contents of a register onto the bus or writing data from the bus into a register memory edit agc core rope memory rom block i agc memory was organized into 1 kiloword banks the lowest bank bank 0 was erasable memory ram all banks above bank 0 were fixed memory rom each agc instruction had a 12 bit address field the lower bits 1 10 addressed the memory inside each bank bits 11 and 12 selected the bank 00 selected the erasable memory bank 01 selected the lowest bank bank 1 of fixed memory 10 selected the next one bank 2 and 11 selected the bank register that could be used to select any bank above 2 banks 1 and 2 were called fixed fixed memory because they were always available regardless of the contents of the bank register banks 3 and above were called fixed switchable because the selected bank was determined by the bank register the block i agc initially had 12 kilowords of fixed memory but this was later increased to 24 kilowords block ii had 36 kilowords of fixed memory and 2 kilowords of erasable memory the agc transferred data to and from memory through the g register in a process called the memory cycle the memory cycle took 12 timing pulses 11 72 μs the cycle began at timing pulse 1 tp1 when the agc loaded the memory address to be fetched into the s register the memory hardware retrieved the data word from memory at the address specified by the s register words from erasable memory were deposited into the g register by timing pulse 6 tp6 words from fixed memory were available by timing pulse 7 the retrieved memory word was then available in the g register for agc access during timing pulses 7 through 10 after timing pulse 10 the data in the g register was written back to memory the agc memory cycle occurred continuously during agc operation instructions needing memory data had to access it during timing pulses 7 10 if the agc changed the memory word in the g register the changed word was written back to memory after timing pulse 10 in this way data words cycled continuously from memory to the g register and then back again to memory the lower 15 bits of each memory word held agc instructions or data with each word being protected by a 16th odd parity bit this bit was set to 1 or 0 by a parity generator circuit so a count of the 1s in each memory word would always produce an odd number a parity checking circuit tested the parity bit during each memory cycle if the bit didn t match the expected value the memory word was assumed to be corrupted and a parity alarm panel light was illuminated interrupts and involuntary counters edit the agc had five vectored interrupts dsrupt was triggered at regular intervals to update the user display dsky erupt was generated by various hardware failures or alarms keyrupt signaled a key press from the user s keyboard t3rrupt was generated at regular intervals from a hardware timer to update the agc s real time clock uprupt was generated each time a 16 bit word of uplink data was loaded into the agc the agc responded to each interrupt by temporarily suspending the current program executing a short interrupt service routine and then resuming the interrupted program the agc also had 20 involuntary counters these were memory locations which functioned as up down counters or shift registers the counters would increment decrement or shift in response to internal inputs the increment pinc decrement minc or shift shinc was handled by one subsequence of microinstructions inserted between any two regular instructions interrupts could be triggered when the counters overflowed the t3rupt and dsrupt interrupts were produced when their counters driven by a 100 hz hardware clock overflowed after executing many pinc subsequences the uprupt interrupt was triggered after its counter executing the shinc subsequence had shifted 16 bits of uplink data into the agc standby mode edit the agc had a power saving mode controlled by a standby allowed switch this mode turned off the agc power except for the 2 048 mhz clock and the scaler the f17 signal from the scaler turned the agc power and the agc back on at 1 28 second intervals in this mode the agc performed essential functions checked the standby allowed switch and if still enabled turned off the power and went back to sleep until the next f17 signal in the standby mode the agc slept most of the time therefore it was not awake to perform the pinc instruction needed to update the agc s real time clock at 10 ms intervals to compensate one of the functions performed by the agc each time it awoke in the standby mode was to update the real time clock by 1 28 seconds the standby mode was designed to reduce power by 5 to 10 w from 70 w during midcourse flight when the agc was not needed however in practice the agc was left on during all phases of the mission and this feature was never used data buses edit the agc had a 16 bit read bus and a 16 bit write bus data from central registers a q z or lp or other internal registers could be gated onto the read bus with a control signal the read bus connected to the write bus through a non inverting buffer so any data appearing on the read bus also appeared on the write bus other control signals could copy write bus data back into the registers data transfers worked like this to move the address of the next instruction from the b register to the s register an rb read b control signal was issued this caused the address to move from register b to the read bus and then to the write bus a ws write s control signal moved the address from the write bus into the s register several registers could be read onto the read bus simultaneously when this occurred data from each register was inclusive or ed onto the bus this inclusive or feature was used to implement the mask instruction which was a logical and operation because the agc had no native ability to do a logical and but could do a logical or through the bu...