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cpu multiplier wikipedia 181 captures 13 sep 2006 03 aug 2026 sep oct nov 16 2021 2022 2023 success fail about this capture timestamps the wayback machine http web archive org web 20221016014519 https en wikipedia org wiki cpu_multiplier cpu multiplier from wikipedia the free encyclopedia jump to navigation jump to search this article has multiple issues please help improve it or discuss these issues on the talk page learn how and when to remove these template messages this article needs to be updated please help update this article to reflect recent events or newly available information october 2019 this article needs additional citations for verification please help improve this article by adding citations to reliable sources unsourced material may be challenged and removed find sources cpu multiplier news newspapers books scholar jstor october 2019 learn how and when to remove this template message learn how and when to remove this template message in computing the clock multiplier or cpu multiplier or bus core ratio sets the ratio of an internal cpu clock rate to the externally supplied clock a cpu with a 10x multiplier will thus see 10 internal cycles produced by pll based frequency multiplier circuitry for every external clock cycle for example a system with an external clock of 100 mhz and a 36x clock multiplier will have an internal cpu clock of 3 6 ghz the external address and data buses of the cpu often collectively termed front side bus fsb in pc contexts also use the external clock as a fundamental timing base however they could also employ a small multiple of this base frequency typically two or four to transfer data faster the internal frequency of microprocessors is usually based on fsb frequency to calculate internal frequency the cpu multiplies bus frequency by a number called the clock multiplier for calculation the cpu uses actual bus frequency and not effective bus frequency to determine the actual bus frequency for processors that use dual data rate ddr buses amd athlon and duron and quad data rate buses all intel microprocessors starting from pentium 4 the effective bus speed should be divided by 2 for amd or 4 for intel clock multipliers on many modern processors are fixed it is usually not possible to change them some versions of processors have clock multipliers unlocked that is they can be overclocked by increasing the clock multiplier setting in the motherboard s bios setup program some cpu engineering samples may also have the clock multiplier unlocked many intel qualification samples have maximum clock multiplier locked these cpus may be underclocked run at lower frequency but they cannot be overclocked by increasing clock multiplier higher than intended by cpu design while these qualification samples and majority of production microprocessors cannot be overclocked by increasing their clock multiplier they still can be overclocked by using a different technique by increasing fsb frequency topology of an older x86 computer notice the fsb connecting the cpu and the northbridge contents 1 basic system structure 1 1 variants 1 2 bios settings 2 clock doubling 3 see also basic system structure edit as of 2009 update computers have several interconnected devices cpu ram peripherals etc see diagram that typically run at different speeds thus they use internal buffers and caches when communicating with each other via the shared buses in the system in pcs the cpu s external address and data buses connect the cpu to the rest of the system via the northbridge nearly every desktop cpu produced since the introduction of the 486dx2 in 1992 has employed a clock multiplier to run its internal logic at a higher frequency than its external bus but still remain synchronous with it this improves the cpu performance by relying on internal cache memories or wide buses often also capable of more than one transfer per clock cycle to make up for the frequency difference variants edit some cpus such as athlon 64 and opteron handle main memory using a separate and dedicated low level memory bus these processors communicate with other devices in the system including other cpus using one or more slightly higher level hypertransport links like the data and address buses in other designs these links employ the external clock for data transfer timing typically 800 mhz or 1 ghz as of 2007 bios settings edit some systems allow owners to change the clock multiplier in the bios menu increasing the clock multiplier will increase the cpu clock speed without affecting the clock speed of other components increasing the external clock and bus speed will affect the cpu as well as ram and other components these adjustments provide the two common methods of overclocking and underclocking a computer perhaps combined with some adjustment of cpu or memory voltages changing oscillator crystals occurs only rarely note that careless overclocking can cause damage to a cpu or other component due to overheating or even voltage breakdown newer cpus often have a locked clock multiplier meaning that the bus speed or the clock multiplier cannot be changed in the bios unless the user hacks the cpu to unlock the multiplier high end cpus however normally have an unlocked clock multiplier clock doubling edit the phrase clock doubling implies a clock multiplier of two examples of clock doubled cpus include the intel 80486dx2 which ran at 50 or 66 mhz on a 25 or 33 mhz bus the weitek sparc power µp a clock doubled 80 mhz version of the sparc processor that one could drop into the otherwise 40 mhz sparcstation 2 in both these cases the overall speed of the systems increased by about 75 citation needed by the late 1990s almost all high performance processors excluding typical embedded systems run at higher speeds than their external buses so the term clock doubling has lost much of its impact for cpu bound applications clock doubling will theoretically improve the overall performance of the machine substantially provided the fetching of data from memory does not prove a bottleneck in more modern processors where the multiplier greatly exceeds two the bandwidth and latency of specific memory ics or the bus or memory controller typically become a limiting factor see also edit overclocking memory divider frequency multiplier retrieved from https en wikipedia org w index php title cpu_multiplier oldid 1049339898 categories clock signal hidden categories wikipedia articles in need of updating from october 2019 all wikipedia articles in need of updating articles needing additional references from october 2019 all articles needing additional references articles with multiple maintenance issues articles containing potentially dated statements from 2009 all articles containing potentially dated statements all articles with unsourced statements articles with unsourced statements from april 2008 navigation menu personal tools not logged in talk contributions create account log in namespaces article talk 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