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cellular architecture wikipedia 138 captures 11 jan 2012 04 sep 2026 sep oct nov 16 2021 2022 2023 success fail about this capture timestamps the wayback machine http web archive org web 20221016120420 https en wikipedia org wiki cellular_architecture cellular architecture from wikipedia the free encyclopedia jump to navigation jump to search type of computer architecture prominent in parallel computing this article does not cite any sources please help improve this article by adding citations to reliable sources unsourced material may be challenged and removed find sources cellular architecture news newspapers books scholar jstor august 2012 learn how and when to remove this template message this article needs to be updated please help update this article to reflect recent events or newly available information january 2017 the cyclops64 architecture will contain many hundreds of computing nodes this article is about the computer architecture for the biological concept see structural biology see also cellular automaton a cellular architecture is a type of computer architecture prominent in parallel computing cellular architectures are relatively new with ibm s cell microprocessor being the first one to reach the market cellular architecture takes multi core architecture design to its logical conclusion by giving the programmer the ability to run large numbers of concurrent threads within a single processor each cell is a compute node containing thread units memory and communication speed up is achieved by exploiting thread level parallelism inherent in many applications cell a cellular architecture containing 9 cores is the processor used in the playstation 3 another prominent cellular architecture is cyclops64 a massively parallel architecture currently under development by ibm cellular architectures follow the low level programming paradigm which exposes the programmer to much of the underlying hardware this allows the programmer to greatly optimize their code for the platform but at the same time makes it more difficult to develop software this computer hardware article is a stub you can help wikipedia by expanding it v t e external links edit cellular architecture builds next generation supercomputers ornl ibm and the blue gene project energy ibm are partners in biological supercomputing project cell based architecture v t e processor technologies models abstract machine stored program computer finite state machine with datapath hierarchical deterministic finite automaton queue automaton cellular automaton quantum cellular automaton turing machine alternating turing machine universal post turing quantum nondeterministic turing machine probabilistic turing machine hypercomputation zeno machine belt machine stack machine register machines counter pointer random access random access stored program architecture microarchitecture von neumann harvard modified dataflow transport triggered cellular endianness memory access numa huma load store register memory cache hierarchy memory hierarchy virtual memory secondary storage heterogeneous fabric multiprocessing cognitive neuromorphic instruction set architectures types orthogonal instruction set cisc risc application specific edge trips vliw epic misc oisc nisc zisc visc architecture quantum computing comparison addressing modes instruction sets motorola 68000 series vax pdp 11 x86 arm stanford mips mips mips x power power powerpc power isa clipper architecture sparc superh dec alpha etrax cris m32r unicore itanium openrisc risc v microblaze lmc system 3x0 s 360 s 370 s 390 z architecture tilera isa visc architecture epiphany architecture others execution instruction pipelining pipeline stall operand forwarding classic risc pipeline hazards data dependency structural control false sharing out of order scoreboarding tomasulo algorithm reservation station re order buffer register renaming wide issue speculative branch prediction memory dependence prediction parallelism level bit bit serial word instruction pipelining scalar superscalar task thread process data vector memory distributed multithreading temporal simultaneous hyperthreading speculative preemptive cooperative flynn s taxonomy sisd simd array processing simt pipelined processing associative processing swar misd mimd spmd processor performance transistor count instructions per cycle ipc cycles per instruction cpi instructions per second ips floating point operations per second flops transactions per second tps synaptic updates per second sups performance per watt ppw cache performance metrics computer performance by orders of magnitude types central processing unit cpu graphics processing unit gpu gpgpu vector barrel stream tile processor coprocessor pal asic fpga fpoa cpld multi chip module mcm system in a package sip package on a package pop by application embedded system microprocessor microcontroller mobile notebook ultra low voltage asip soft microprocessor systems on chip system on a chip soc multiprocessor mpsoc programmable psoc network on a chip noc hardware accelerators coprocessor ai accelerator graphics processing unit gpu image processor vision processing unit vpu physics processing unit ppu digital signal processor dsp tensor processing unit tpu secure cryptoprocessor network processor baseband processor word size 1 bit 4 bit 8 bit 12 bit 15 bit 16 bit 24 bit 32 bit 48 bit 64 bit 128 bit 256 bit 512 bit bit slicing others variable core count single core multi core manycore heterogeneous architecture components core cache cpu cache scratchpad memory data cache instruction cache replacement policies coherence bus clock rate clock signal fifo functional units arithmetic logic unit alu address generation unit agu floating point unit fpu memory management unit mmu load store unit translation lookaside buffer tlb branch predictor branch target predictor integrated memory controller imc memory management unit instruction decoder logic combinational sequential glue logic gate quantum array registers processor register status register stack register register file memory buffer memory address register program counter control unit hardwired control unit instruction unit data buffer write buffer microcode rom horizontal microcode counter datapath multiplexer demultiplexer adder multiplier cpu binary decoder address decoder sum addressed decoder barrel shifter circuitry integrated circuit 3d mixed signal power management boolean digital analog quantum switch power management pmu apm acpi dynamic frequency scaling dynamic voltage scaling clock gating performance per watt ppw related history of general purpose cpus microprocessor chronology processor design digital electronics hardware security module semiconductor device fabrication tick tock model pin grid array chip carrier retrieved from https en wikipedia org w index php title cellular_architecture oldid 1098936943 categories computer hardware stubs parallel computing computer architecture classes of computers hidden categories articles with short description short description matches wikidata articles lacking sources from august 2012 all articles lacking sources wikipedia articles in need of updating from january 2017 all wikipedia articles in need of updating all stub articles navigation menu personal tools not logged in talk contributions create account log in namespaces article talk english views read edit view history more search navigation main page contents current events random article about wikipedia contact us donate contribute help learn to edit community portal recent changes upload file tools what links here related changes upload file special pages permanent link page information cite this page wikidata item print export download as pdf printable version languages العربية فارسی italiano edit links this page was last edited on 18 july 2022 at 06 02 utc text is available under the creative commons attribution sharealike license 3 0 additional terms may apply by using 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