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the free encyclopedia redirected from demultiplexer jump to navigation jump to search a device that selects between several analog or digital input signals this article is about electronics switching for telecommunications see multiplexing schematic of a 2 to 1 multiplexer it can be equated to a controlled switch schematic of a 1 to 2 demultiplexer like a multiplexer it can be equated to a controlled switch in electronics a multiplexer or mux spelled sometimes as multiplexor also known as a data selector is a device that selects between several analog or digital input signals and forwards the selected input to a single output line 1 the selection is directed by a separate set of digital inputs known as select lines a multiplexer of 2 n displaystyle 2 n inputs has n displaystyle n select lines which are used to select which input line to send to the output 2 a multiplexer makes it possible for several input signals to share one device or resource for example one analog to digital converter or one communications transmission medium instead of having one device per input signal multiplexers can also be used to implement boolean functions of multiple variables conversely a demultiplexer or demux is a device taking a single input and selecting signals of the output of the compatible mux which is connected to the single input and a shared selection line a multiplexer is often used with a complementary demultiplexer on the receiving end 1 an electronic multiplexer can be considered as a multiple input single output switch and a demultiplexer as a single input multiple output switch 3 the schematic symbol for a multiplexer is an isosceles trapezoid with the longer parallel side containing the input pins and the short parallel side containing the output pin 4 the schematic on the right shows a 2 to 1 multiplexer on the left and an equivalent switch on the right the s e l displaystyle sel wire connects the desired input to the output contents 1 applications 2 digital multiplexers 2 1 chaining multiplexers 2 2 list of ics which provide multiplexing 3 digital demultiplexers 3 1 list of ics which provide demultiplexing 4 multiplexers as plds 5 see also 6 references 7 further reading 8 external links applications edit multiplexers are part of computer systems to select data from a specific source be it a memory chip or a hardware peripheral a computer uses multiplexers to control the data and address buses allowing the processor to select data from multiple data sources the basic function of a multiplexer combining multiple inputs into a single data stream on the receiving side a demultiplexer splits the single data stream into the original multiple signals in digital communications multiplexers allow several connections over a single channel by connecting the multiplexer s single output to the demultiplexer s single input time division multiplexing the image to the right demonstrates this benefit in this case the cost of implementing separate channels for each data source is higher than the cost and inconvenience of providing the multiplexing demultiplexing functions at the receiving end of the data link a complementary demultiplexer is usually required to break the single data stream back down into the original streams in some cases the far end system may have functionality greater than a simple demultiplexer and while the demultiplexing still occurs technically it may never be implemented discretely this would be the case when for instance a multiplexer serves a number of ip network users and then feeds directly into a router which immediately reads the content of the entire link into its routing processor and then does the demultiplexing in memory from where it will be converted directly into ip sections often a multiplexer and demultiplexer are combined into a single piece of equipment which is simply referred to as a multiplexer both circuit elements are needed at both ends of a transmission link because most communications systems transmit in both directions in analog circuit design a multiplexer is a special type of analog switch that connects one signal selected from several inputs to a single output digital multiplexers edit in digital circuit design the selector wires are of digital value in the case of a 2 to 1 multiplexer a logic value of 0 would connect i 0 displaystyle i_ 0 to the output while a logic value of 1 would connect i 1 displaystyle i_ 1 to the output in larger multiplexers the number of selector pins is equal to log 2 n displaystyle left lceil log _ 2 n right rceil where n displaystyle n is the number of inputs for example 9 to 16 inputs would require no fewer than 4 selector pins and 17 to 32 inputs would require no fewer than 5 selector pins the binary value expressed on these selector pins determines the selected input pin a 2 to 1 multiplexer has a boolean equation where a displaystyle a and b displaystyle b are the two inputs s 0 displaystyle s_ 0 is the selector input and z displaystyle z is the output z a s 0 b s 0 displaystyle z a wedge neg s_ 0 vee b wedge s_ 0 a 2 to 1 mux which can be expressed as a truth table s 0 displaystyle s_ 0 a displaystyle a b displaystyle b z displaystyle z 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 or in simpler notation s 0 displaystyle s_ 0 z displaystyle z 0 a 1 b these tables show that when s 0 0 displaystyle s_ 0 0 then z a displaystyle z a but when s 0 1 displaystyle s_ 0 1 then z b displaystyle z b a straightforward realization of this 2 to 1 multiplexer would need 2 and gates an or gate and a not gate while this is mathematically correct a direct physical implementation would be prone to race conditions that require additional gates to suppress 5 larger multiplexers are also common and as stated above require log 2 n displaystyle left lceil log _ 2 n right rceil selector pins for n displaystyle n inputs other common sizes are 4 to 1 8 to 1 and 16 to 1 since digital logic uses binary values powers of 2 are used 4 8 16 to maximally control a number of inputs for the given number of selector inputs 4 to 1 mux 8 to 1 mux 16 to 1 mux the boolean equation for a 4 to 1 multiplexer is z a s 0 s 1 b s 0 s 1 c s 0 s 1 d s 0 s 1 displaystyle z a wedge neg s_ 0 wedge neg s_ 1 vee b wedge s_ 0 wedge neg s_ 1 vee c wedge neg s_ 0 wedge s_ 1 vee d wedge s_ 0 wedge s_ 1 the following 4 to 1 multiplexer is constructed from 3 state buffers and and gates the and gates are acting as the decoder a 4 1 mux circuit using 3 input and and other gates the subscripts on the i n displaystyle i_ n inputs indicate the decimal value of the binary control inputs at which that input is let through chaining multiplexers edit larger multiplexers can be constructed by using smaller multiplexers by chaining them together for example an 8 to 1 multiplexer can be made with two 4 to 1 and one 2 to 1 multiplexers the two 4 to 1 multiplexer outputs are fed into the 2 to 1 with the selector pins on the 4 to 1 s put in parallel giving a total number of selector inputs to 3 which is equivalent to an 8 to 1 list of ics which provide multiplexing edit signetics s54s157 quad 2 1 mux for 7400 series part numbers in the following table x is the logic family ic no function output state 74x157 quad 2 1 mux output same as input given 74x158 quad 2 1 mux output is inverted input 74x153 dual 4 1 mux output same as input 74x352 dual 4 1 mux output is inverted input 74x151a 8 1 mux both outputs available i e complementary outputs 74x151 8 1 mux output is inverted input 74x150 16 1 mux output is inverted input digital demultiplexers edit see also inverse multiplexer demultiplexers take one data input and a number of selection inputs and they have several outputs they forward the data input to one of the outputs depending on the values of the selection inputs demultiplexers are sometimes convenient for designing general purpose logic because if the demultiplexer s input is always true the demultiplexer acts as a binary decoder this means that any function of the selection bits can be constructed by logically or ing the correct set of outputs if x is the input and s is the selector and a and b are the outputs a x s displaystyle a x wedge neg s b x s displaystyle b x wedge s example a single bit 1 to 4 line demultiplexer list of ics which provide demultiplexing edit fairchild 74f138 1 8 demultiplexer for 7400 series part numbers in the following table x is the logic family ic no 7400 ic no 4000 function output state 74x139 dual 1 4 demux output is inverted input 74x156 dual 1 4 demux output is open collector 74x138 1 8 demux output is inverted input 74x238 1 8 demux 74x154 1 16 demux output is inverted input 74x159 cd4514 15 1 16 demux output is open collector and same as input multiplexers as plds edit multiplexers can also be used as programmable logic devices to implement boolean functions any boolean function of n variables and one result can be implemented with a multiplexer with n selector inputs the variables are connected to the selector inputs and the function result 0 or 1 for each possible combination of selector inputs is connected to the corresponding data input if one of the variables for example d is also available inverted a multiplexer with n 1 selector inputs is sufficient the data inputs are connected to 0 1 d or d according to the desired output for each combination of the selector inputs 6 see also edit digital subscriber line access multiplexer dslam inverse multiplexer multiplexing code division multiplexing frequency division multiplexing time division multiplexing wavelength division multiplexing statistical multiplexing charlieplexing priority encoder rule 184 a cellular automaton in which each cell acts as a multiplexer for the values from the two adjacent cells statistical multiplexer references edit a b dean tamara 2010 network guide to networks delmar pp 82 85 isbn 978 1423902454 debashis de 2010 basic electronics dorling kindersley p 557 isbn 9788131710685 lipták béla 2002 instrument engineers handbook process software and digital networks crc press p 343 isbn 9781439863442 harris david 2007 digital design and computer architecture penrose p 79 isbn 9780080547060 crowe john hayes gill barrie 1998 the multiplexer hazard introduction to digital electronics elsevier pp 111 3 isbn 9780080534992 lancaster donald e 1974 the ttl cookbook h w sams pp 140 3 isbn 9780672210358 further reading edit mano m morris kime charles r 2008 logic and computer design fundamentals 4th ed prentice hall isbn 978 0 13 198926 9 external links edit wikimedia commons has media related to multiplexers the dictionary definition of multiplexer at wiktionary v t e processor technologies models abstract machine stored program computer finite state machine with datapath hierarchical deterministic finite automaton queue automaton cellular automaton quantum cellular automaton turing machine alternating turing machine universal post turing quantum nondeterministic turing machine probabilistic turing machine hypercomputation zeno machine belt machine stack machine register machines counter pointer random access random access stored program architecture microarchitecture von neumann harvard modified dataflow transport triggered cellular endianness memory access numa huma load store register memory cache hierarchy memory hierarchy virtual memory secondary storage heterogeneous fabric multiprocessing cognitive neuromorphic instruction set architectures types orthogonal instruction set cisc risc application specific edge trips vliw epic misc oisc nisc zisc visc architecture quantum computing comparison addressing modes instruction sets motorola 68000 series vax pdp 11 x86 arm stanford mips mips mips x power power powerpc power isa clipper architecture sparc superh dec alpha etrax cris m32r unicore itanium openrisc risc v microblaze lmc system 3x0 s 360 s 370 s 390 z architecture tilera isa visc architecture epiphany architecture others execution instruction pipelining pipeline stall operand forwarding classic risc pipeline hazards data dependency structural control false sharing out of order scoreboarding tomasulo algorithm reservation station re order buffer register renaming wide issue speculative branch prediction memory dependence prediction parallelism level bit bit serial word instruction pipelining scalar superscalar task thread process data vector memory distributed multithreading temporal simultaneous hyperthreading speculative preemptive cooperative flynn s taxonomy sisd simd array processing simt pipelined processing associative processing swar misd mimd spmd processor performance transistor count instructions per cycle ipc cycles per instruction cpi instructions per second ips floating point operations per second flops transactions per second tps synaptic updates per second sups performance per watt ppw cache performance metrics computer performance by orders of magnitude types central processing unit cpu graphics processing unit gpu gpgpu vector barrel stream tile processor coprocessor pal asic fpga fpoa cpld multi chip module mcm system in a package sip package on a package pop by application embedded system microprocessor microcontroller mobile notebook ultra low voltage asip soft microprocessor systems on chip system on a chip soc multiprocessor mpsoc programmable psoc network on a chip noc hardware accelerators coprocessor ai accelerator graphics processing unit gpu image processor vision processing unit vpu physics processing unit ppu digital signal processor dsp tensor processing unit tpu secure cryptoprocessor network processor baseband processor word size 1 bit 4 bit 8 bit 12 bit 15 bit 16 bit 24 bit 32 bit 48 bit 64 bit 128 bit 256 bit 512 bit bit slicing others variable core count single core multi core manycore heterogeneous architecture components core cache cpu cache scratchpad memory data cache instruction cache replacement policies coherence bus clock rate clock signal fifo functional units arithmetic logic unit alu address generation unit agu floating point unit fpu memory management unit mmu load store unit translation lookaside buffer tlb branch predictor branch target predictor integrated memory controller imc memory management unit instruction decoder logic combinational sequential glue logic gate quantum array registers processor register status register stack register register file memory buffer memory address register program counter control unit hardwired control unit instruction unit data buffer write buffer microcode rom horizontal microcode counter datapath multiplexer demultiplexer adder multiplier cpu binary decoder address decoder sum addressed decoder barrel shifter circuitry integrated circuit 3d mixed signal power management boolean digital analog quantum switch power management pmu apm acpi dynamic frequency scaling dynamic voltage scaling clock gating performance per watt ppw related history of general purpose cpus microprocessor chronology processor desig...