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fifo computing and electronics wikipedia 528 captures 20 mar 2015 18 sep 2026 sep oct nov 16 2021 2022 2023 success fail about this capture timestamps the wayback machine http web archive org web 20221016011338 https en wikipedia org wiki fifo_ computing_and_electronics fifo computing and electronics from wikipedia the free encyclopedia jump to navigation jump to search scheduling algorithm the first piece of data inserted into a queue is processed first this article needs additional citations for verification please help improve this article by adding citations to reliable sources unsourced material may be challenged and removed find sources fifo computing and electronics news newspapers books scholar jstor march 2015 learn how and when to remove this template message representation of a fifo queue in computing and in systems theory fifo is an acronym for first in first out the first in is the first out a method for organizing the manipulation of a data structure often specifically a data buffer where the oldest first entry or head of the queue is processed first such processing is analogous to servicing people in a queue area on a first come first served fcfs basis i e in the same sequence in which they arrive at the queue s tail fcfs is also the jargon term for the fifo operating system scheduling algorithm which gives every process central processing unit cpu time in the order in which it is demanded 1 fifo s opposite is lifo last in first out where the youngest entry or top of the stack is processed first 2 a priority queue is neither fifo or lifo but may adopt similar behaviour temporarily or by default queueing theory encompasses these methods for processing data structures as well as interactions between strict fifo queues contents 1 computer science 2 electronics 2 1 synchronicity 2 2 status flags 3 see also 4 references 5 external links computer science edit representation of a fifo queue with enqueue and dequeue operations depending on the application a fifo could be implemented as a hardware shift register or using different memory structures typically a circular buffer or a kind of list for information on the abstract data structure see queue data structure most software implementations of a fifo queue are not thread safe and require a locking mechanism to verify the data structure chain is being manipulated by only one thread at a time the following code shows a linked list fifo c language implementation in practice a number of list implementations exist including popular unix systems c sys queue h macros or the c standard library std list template avoiding the need for implementing the data structure from scratch include memory include stdexcept using namespace std template typename t class fifo struct node t value shared_ptr node next nullptr node t _value value _value shared_ptr node front nullptr shared_ptr node back nullptr public void enqueue t _value if front nullptr front make_shared node _value back front else back next make_shared node _value back back next t dequeue if front nullptr throw underflow_error nothing to dequeue t value front value front move front next return value in computing environments that support the pipes and filters model for interprocess communication a fifo is another name for a named pipe disk controllers can use the fifo as a disk scheduling algorithm to determine the order in which to service disk i o requests where it is also known by the same fcfs initialism as for cpu scheduling mentioned before 1 communication network bridges switches and routers used in computer networks use fifos to hold data packets in route to their next destination typically at least one fifo structure is used per network connection some devices feature multiple fifos for simultaneously and independently queuing different types of information 3 electronics edit a fifo schedule fifos are commonly used in electronic circuits for buffering and flow control between hardware and software in its hardware form a fifo primarily consists of a set of read and write pointers storage and control logic storage may be static random access memory sram flip flops latches or any other suitable form of storage for fifos of non trivial size a dual port sram is usually used where one port is dedicated to writing and the other to reading the first known fifo implemented in electronics was by peter alfke in 1969 at fairchild semiconductor 4 alfke was later a director at xilinx synchronicity edit a synchronous fifo is a fifo where the same clock is used for both reading and writing an asynchronous fifo uses different clocks for reading and writing and they can introduce metastability issues a common implementation of an asynchronous fifo uses a gray code or any unit distance code for the read and write pointers to ensure reliable flag generation one further note concerning flag generation is that one must necessarily use pointer arithmetic to generate flags for asynchronous fifo implementations conversely one may use either a leaky bucket approach or pointer arithmetic to generate flags in synchronous fifo implementations a hardware fifo is used for synchronization purposes it is often implemented as a circular queue and thus has two pointers read pointer read address register write pointer write address register status flags edit examples of fifo status flags include full empty almost full and almost empty a fifo is empty when the read address register reaches the write address register a fifo is full when the write address register reaches the read address register read and write addresses are initially both at the first memory location and the fifo queue is empty in both cases the read and write addresses end up being equal to distinguish between the two situations a simple and robust solution is to add one extra bit for each read and write address which is inverted each time the address wraps with this set up the disambiguation conditions are when the read address register equals the write address register the fifo is empty when the read and write address registers differ only in the extra most significant bit and the rest are equal the fifo is full see also edit fifo and lifo accounting fino queueing theory references edit a b andrew s tanenbaum herbert bos 2015 modern operating systems pearson isbn 978 0 13 359162 0 kruse robert l 1987 1984 data structures program design second edition joan l stone kenny beck ed o dougherty production process staff workers second hc textbook ed englewood cliffs new jersey 07632 prentice hall inc div of simon schuster p 150 isbn 0 13 195884 4 cite book cs1 maint location link james f kurose keith w ross july 2006 computer networking a top down approach addison wesley isbn 978 0 321 41849 4 peter alfke s post at comp arch fpga on 19 jun 1998 external links edit cummings et al simulation and synthesis techniques for asynchronous fifo design with asynchronous pointer comparisons snug san jose 2002 authority control national libraries germany v t e queueing theory single queueing nodes d m 1 queue m d 1 queue m d c queue m m 1 queue burke s theorem m m c queue m m queue m g 1 queue pollaczek khinchine formula matrix analytic method m g k queue g m 1 queue g g 1 queue kingman s formula lindley equation fork join queue bulk queue arrival processes poisson point process markovian arrival process rational arrival process queueing networks jackson network traffic equations gordon newell theorem mean value analysis buzen s algorithm kelly network g network bcmp network service policies fifo lifo processor sharing round robin shortest job next shortest remaining time key concepts continuous time markov chain kendall s notation little s law product form solution balance equation quasireversibility flow equivalent server method arrival theorem decomposition method beneš method limit theorems fluid limit mean field theory heavy traffic approximation reflected brownian motion extensions fluid queue layered queueing network polling system adversarial queueing network loss network retrial queue information systems data buffer erlang unit erlang distribution flow control data message queue network congestion network scheduler pipeline software quality of service scheduling computing teletraffic engineering category retrieved from https en wikipedia org w index php title fifo_ computing_and_electronics oldid 1104188471 categories scheduling algorithms queue management inter process communication hidden categories cs1 maint location articles with short description short description is different from wikidata articles needing additional references from march 2015 all articles needing additional references articles with gnd identifiers navigation menu personal tools not logged in talk contributions create account log in namespaces article talk english views read edit view history more search navigation main page contents current events random article about wikipedia contact us donate contribute help learn to edit community portal recent changes upload file tools what links here related changes upload file special pages permanent link page information cite this page wikidata item print export download as pdf printable version languages bosanski català čeština deutsch eesti español euskara فارسی français 한국어 bahasa indonesia íslenska italiano עברית latviešu lietuvių lombard македонски монгол nederlands 日本語 português русский shqip српски srpski svenska türkçe українська 粵語 中文 edit links this page was last edited on 13 august 2022 at 09 01 utc text is available under the creative commons attribution sharealike license 3 0 additional terms may apply by using this site you agree to the terms of use and privacy policy wikipedia is a registered trademark of the wikimedia foundation inc a non profit organization privacy policy about wikipedia disclaimers contact wikipedia mobile view developers statistics cookie statement