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in recent years load store architectures vliw and epic types have been in fashion architectures that are dealing with data parallelism include simd and vectors some labels used to denote classes of cpu architectures are not particularly descriptive especially so the cisc label many early designs retroactively denoted cisc are in fact significantly simpler than modern risc processors in several respects however the choice of instruction set architecture may greatly affect the complexity of implementing high performance devices the prominent strategy used to develop the first risc processors was to simplify instructions to a minimum of individual semantic complexity combined with high encoding regularity and simplicity such uniform instructions were easily fetched decoded and executed in a pipelined fashion and a simple strategy to reduce the number of logic levels in order to reach high operating frequencies instruction cache memories compensated for the higher operating frequency and inherently low code density while large register sets were used to factor out as much of the slow memory accesses as possible instruction pipelining edit main article instruction pipelining one of the first and most powerful techniques to improve performance is the use of instruction pipelining early processor designs would carry out all of the steps above for one instruction before moving onto the next large portions of the circuitry were left idle at any one step for instance the instruction decoding circuitry would be idle during execution and so on pipelining improves performance by allowing a number of instructions to work their way through the processor at the same time in the same basic example the processor would start to decode step 1 a new instruction while the last one was waiting for results this would allow up to four instructions to be in flight at one time making the processor look four times as fast although any one instruction takes just as long to complete there are still four steps the cpu as a whole retires instructions much faster risc makes pipelines smaller and much easier to construct by cleanly separating each stage of the instruction process and making them take the same amount of time one cycle the processor as a whole operates in an assembly line fashion with instructions coming in one side and results out the other due to the reduced complexity of the classic risc pipeline the pipelined core and an instruction cache could be placed on the same size die that would otherwise fit the core alone on a cisc design this was the real reason that risc was faster early designs like the sparc and mips often ran over 10 times as fast as intel and motorola cisc solutions at the same clock speed and price pipelines are by no means limited to risc designs by 1986 the top of the line vax implementation vax 8800 was a heavily pipelined design slightly predating the first commercial mips and sparc designs most modern cpus even embedded cpus are now pipelined and microcoded cpus with no pipelining are seen only in the most area constrained embedded processors examples needed large cisc machines from the vax 8800 to the modern pentium 4 and athlon are implemented with both microcode and pipelines improvements in pipelining and caching are the two major microarchitectural advances that have enabled processor performance to keep pace with the circuit technology on which they are based cache edit main article cpu cache it was not long before improvements in chip manufacturing allowed for even more circuitry to be placed on the die and designers started looking for ways to use it one of the most common was to add an ever increasing amount of cache memory on die cache is very fast and expensive memory it can be accessed in a few cycles as opposed to many needed to talk to main memory the cpu includes a cache controller which automates reading and writing from the cache if the data is already in the cache it is accessed from there at considerable time savings whereas if it is not the processor is stalled while the cache controller reads it in risc designs started adding cache in the mid to late 1980s often only 4 kb in total this number grew over time and typical cpus now have at least 2 mb while more powerful cpus come with 4 or 6 or 12mb or even 32mb or more with the most being 768mb in the newly released epyc milan x line organized in multiple levels of a memory hierarchy generally speaking more cache means more performance due to reduced stalling caches and pipelines were a perfect match for each other previously it didn t make much sense to build a pipeline that could run faster than the access latency of off chip memory using on chip cache memory instead meant that a pipeline could run at the speed of the cache access latency a much smaller length of time this allowed the operating frequencies of processors to increase at a much faster rate than that of off chip memory branch prediction edit main article branch predictor one barrier to achieving higher performance through instruction level parallelism stems from pipeline stalls and flushes due to branches normally whether a conditional branch will be taken isn t known until late in the pipeline as conditional branches depend on results coming from a register from the time that the processor s instruction decoder has figured out that it has encountered a conditional branch instruction to the time that the deciding register value can be read out the pipeline needs to be stalled for several cycles or if it s not and the branch is taken the pipeline needs to be flushed as clock speeds increase the depth of the pipeline increases with it and some modern processors may have 20 stages or more on average every fifth instruction executed is a branch so without any intervention that s a high amount of stalling techniques such as branch prediction and speculative execution are used to lessen these branch penalties branch prediction is where the hardware makes educated guesses on whether a particular branch will be taken in reality one side or the other of the branch will be called much more often than the other modern designs have rather complex statistical prediction systems which watch the results of past branches to predict the future with greater accuracy the guess allows the hardware to prefetch instructions without waiting for the register read speculative execution is a further enhancement in which the code along the predicted path is not just prefetched but also executed before it is known whether the branch should be taken or not this can yield better performance when the guess is good with the risk of a huge penalty when the guess is bad because instructions need to be undone superscalar edit main article superscalar even with all of the added complexity and gates needed to support the concepts outlined above improvements in semiconductor manufacturing soon allowed even more logic gates to be used in the outline above the processor processes parts of a single instruction at a time computer programs could be executed faster if multiple instructions were processed simultaneously this is what superscalar processors achieve by replicating functional units such as alus the replication of functional units was only made possible when the die area of a single issue processor no longer stretched the limits of what could be reliably manufactured by the late 1980s superscalar designs started to enter the market place in modern designs it is common to find two load units one store many instructions have no results to store two or more integer math units two or more floating point units and often a simd unit of some sort the instruction issue logic grows in complexity by reading in a huge list of instructions from memory and handing them off to the different execution units that are idle at that point the results are then collected and re ordered at the end out of order execution edit main article out of order execution the addition of caches reduces the frequency or duration of stalls due to waiting for data to be fetched from the memory hierarchy but does not get rid of these stalls entirely in early designs a cache miss would force the cache controller to stall the processor and wait of course there may be some other instruction in the program whose data is available in the cache at that point out of order execution allows that ready instruction to be processed while an older instruction waits on the cache then re orders the results to make it appear that everything happened in the programmed order this technique is also used to avoid other operand dependency stalls such as an instruction awaiting a result from a long latency floating point operation or other multi cycle operations register renaming edit main article register renaming register renaming refers to a technique used to avoid unnecessary serialized execution of program instructions because of the reuse of the same registers by those instructions suppose we have two groups of instruction that will use the same register one set of instructions is executed first to leave the register to the other set but if the other set is assigned to a different similar register both sets of instructions can be executed in parallel or in series multiprocessing and multithreading edit main articles multiprocessing and multithreading computer architecture computer architects have become stymied by the growing mismatch in cpu operating frequencies and dram access times none of the techniques that exploited instruction level parallelism ilp within one program could make up for the long stalls that occurred when data had to be fetched from main memory additionally the large transistor counts and high operating frequencies needed for the more advanced ilp techniques required power dissipation levels that could no longer be cheaply cooled for these reasons newer generations of computers have started to exploit higher levels of parallelism that exist outside of a single program or program thread this trend is sometimes known as throughput computing this idea originated in the mainframe market where online transaction processing emphasized not just the execution speed of one transaction but the capacity to deal with massive numbers of transactions with transaction based applications such as network routing and web site serving greatly increasing in the last decade the computer industry has re emphasized capacity and throughput issues one technique of how this parallelism is achieved is through multiprocessing systems computer systems with multiple cpus once reserved for high end mainframes and supercomputers small scale 2 8 multiprocessors servers have become commonplace for the small business market for large corporations large scale 16 256 multiprocessors are common even personal computers with multiple cpus have appeared since the 1990s with further transistor size reductions made available with semiconductor technology advances multi core cpus have appeared where multiple cpus are implemented on the same silicon chip initially used in chips targeting embedded markets where simpler and smaller cpus would allow multiple instantiations to fit on one piece of silicon by 2005 semiconductor technology allowed dual high end desktop cpus cmp chips to be manufactured in volume some designs such as sun microsystems ultrasparc t1 have reverted to simpler scalar in order designs in order to fit more processors on one piece of silicon another technique that has become more popular recently is multithreading in multithreading when the processor has to fetch data from slow system memory instead of stalling for the data to arrive the processor switches to another program or program thread which is ready to execute though this does not speed up a particular program thread it increases the overall system throughput by reducing the time the cpu is idle conceptually multithreading is equivalent to a context switch at the operating system level the difference is that a multithreaded cpu can do a thread switch in one cpu cycle instead of the hundreds or thousands of cpu cycles a context switch normally requires this is achieved by replicating the state hardware such as the register file and program counter for each active thread a further enhancement is simultaneous multithreading this technique allows superscalar cpus to execute instructions from different programs threads simultaneously in the same cycle see also edit electronics portal wikimedia commons has media related to microarchitectures control unit hardware architecture hardware description language hdl instruction level parallelism ilp list of amd cpu microarchitectures list of intel cpu microarchitectures processor design stream processing vhdl very large scale integration vlsi verilog references edit curriculum guidelines for undergraduate degree programs in computer engineering pdf association for computing machinery 2004 p 60 archived from the original pdf on 2017 07 03 comments on computer architecture and organization computer architecture is a key component of computer engineering and the practicing computer engineer should have a practical understanding of this topic murdocca miles heuring vincent 2007 computer architecture and organization an integrated approach wiley p 151 isbn 9780471733881 clements alan principles of computer hardware 4th ed pp 1 2 flynn michael j 2007 an introduction to architecture and machines computer architecture pipelined and parallel processor design jones and bartlett pp 1 3 isbn 9780867202045 a b hennessy john l patterson david a 2006 computer architecture a quantitative approach 4th ed morgan kaufmann isbn 0 12 370490 1 wilkes m v 1969 the growth of interest in microprogramming a literature survey acm computing surveys 1 3 139 145 doi 10 1145 356551 356553 s2cid 10673679 further reading edit patterson d hennessy j 2004 computer organization and design the hardware software interface morgan kaufmann isbn 1 55860 604 1 hamacher v c vrasenic z g zaky s g 2001 computer organization mcgraw hill isbn 0 07 232086 9 stallings william 2002 computer organization and architecture prentice hall isbn 0 13 035119 9 hayes j p 2002 computer architecture and organization mcgraw hill isbn 0 07 286198 3 schneider gary michael 1985 the principles of computer organization wiley pp 6 7 isbn 0 471 88552 5 mano m morris 1992 computer system architecture prentice hall p 3 isbn 0 13 175563 3 abd el barr mostafa el rewini hesham 2004 fundamentals of computer organization and architecture wiley p 1 isbn 0 471 46741 3 gardner j 2001 pc processor microarchitecture extremetech gilreath william f laplante phillip a 2012 2003 computer architecture a minimalist perspective springer isbn 978 1 4615 0237 1 patterson david a 10 october 2018 a new golden age for computer architecture us berkeley acm a m turing laureate colloquium ctwj53r07yi v t e processor technologies models abstract machine stored pr...