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speculative execution wikipedia 525 captures 10 may 2004 01 sep 2026 sep oct nov 17 2021 2022 2023 success fail about this capture timestamps the wayback machine http web archive org web 20221017062212 http en wikipedia org wiki speculative_execution speculative execution from wikipedia the free encyclopedia jump to navigation jump to search optimization technique this article uses bare urls which are uninformative and vulnerable to link rot please consider converting them to full citations to ensure the article remains verifiable and maintains a consistent citation style several templates and tools are available to assist in formatting such as reflinks documentation refill documentation and citation bot documentation september 2022 learn how and when to remove this template message speculative execution is an optimization technique where a computer system performs some task that may not be needed work is done before it is known whether it is actually needed so as to prevent a delay that would have to be incurred by doing the work after it is known that it is needed if it turns out the work was not needed after all most changes made by the work are reverted and the results are ignored the objective is to provide more concurrency if extra resources are available this approach is employed in a variety of areas including branch prediction in pipelined processors value prediction for exploiting value locality prefetching memory and files and optimistic concurrency control in database systems 1 2 3 speculative multithreading is a special case of speculative execution contents 1 overview 2 variants 2 1 eager execution 2 2 predictive execution 3 related concepts 3 1 lazy execution 4 security vulnerabilities 5 see also 6 references overview edit modern pipelined microprocessors use speculative execution to reduce the cost of conditional branch instructions using schemes that predict the execution path of a program based on the history of branch executions 2 in order to improve performance and utilization of computer resources instructions can be scheduled at a time when it has not yet been determined that the instructions will need to be executed ahead of a branch 4 variants edit speculative computation was a related earlier concept 5 eager execution edit see also eager evaluation eager execution is a form of speculative execution where both sides of the conditional branch are executed however the results are committed only if the predicate is true with unlimited resources eager execution also known as oracle execution would in theory provide the same performance as perfect branch prediction with limited resources eager execution should be employed carefully since the number of resources needed grows exponentially with each level of branch executed eagerly 6 predictive execution edit see also pipeline computing main article branch predictor predictive execution is a form of speculative execution where some outcome is predicted and execution proceeds along the predicted path until the actual result is known if the prediction is true the predicted execution is allowed to commit however if there is a misprediction execution has to be unrolled and re executed common forms of this include branch predictors and memory dependence prediction a generalized form is sometimes referred to as value prediction 7 related concepts edit lazy execution edit main article lazy evaluation lazy execution is the opposite of eager execution and does not involve speculation the incorporation of speculative execution into implementations of the haskell programming language a lazy language is a current research topic eager haskell a variant of the language is designed around the idea of speculative execution a 2003 phd thesis made ghc support a kind of speculative execution with an abortion mechanism to back out in case of a bad choice called optimistic execution 8 it was deemed too complicated 9 security vulnerabilities edit starting in 2017 a series of security vulnerabilities were found in the implementations of speculative execution on common processor architectures which effectively enabled an elevation of privileges these include foreshadow meltdown microarchitectural data sampling spectre spoiler pacman see also edit branch predictor out of order execution slipstream computer science speculative multithreading hardware security bug transient execution cpu vulnerabilities references edit lazy and speculative execution butler lampson microsoft research opodis bordeaux france 12 december 2006 a b international business machines corporation research division prabhakar raghavan hadas schachnai mira yaniv 1998 dynamic schemes for speculative execution of code ibm retrieved 18 january 2011 kung h t john t robinson june 1981 on optimistic methods for concurrency control pdf acm trans database syst vol 6 archived pdf from the original on august 31 2019 bernd krieg brückner 1992 esop 92 4th european symposium on programming rennes france february 26 28 1992 proceedings springer pp 56 57 isbn 978 3 540 55253 6 retrieved 18 january 2011 randy b osborne 1990 03 21 speculative computation in multilisp parallel lisp languages and systems ps lecture notes in computer science vol 441 digital equipment corporation research lab pp 103 137 doi 10 1007 bfb0024152 isbn 3 540 52782 6 retrieved 2018 01 26 jurij šilc borut robič theo ungerer 1999 processor architecture from dataflow to superscalar and beyond springer pp 148 150 isbn 978 3 540 64798 0 retrieved 21 january 2011 mark d hill norman p jouppi gourindar s sohi 2000 readings in computer architecture morgan kaufman isbn 9781558605398 retrieved 5 january 2018 jones simon peyton ennals robert 1 august 2003 optimistic evaluation a fast evaluation strategy for non strict programs retrieved 15 may 2019 via www microsoft com cite journal cite journal requires journal help https mail haskell org pipermail haskell 2006 august 018424 html v t e speculative execution security vulnerabilities variants bounds check bypass spectre variant 1 bounds check bypass store spectre ng branch target injection spectre variant 2 foreshadow lazy fp state restore spectre ng load value injection microarchitectural data sampling pacman retbleed rogue data cache load meltdown variant 3 rogue system register read spectre ng variant 3a speculative store bypass spectre ng variant 4 spoiler topics cache side channel attack hardware security bug speculative execution transient execution cpu vulnerabilities v t e processor technologies models abstract machine stored program computer finite state machine with datapath hierarchical deterministic finite automaton queue automaton cellular automaton quantum cellular automaton turing machine alternating turing machine universal post turing quantum nondeterministic turing machine probabilistic turing machine hypercomputation zeno machine belt machine stack machine register machines counter pointer random access random access stored program architecture microarchitecture von neumann harvard modified dataflow transport triggered cellular endianness memory access numa huma load store register memory cache hierarchy memory hierarchy virtual memory secondary storage heterogeneous fabric multiprocessing cognitive neuromorphic instruction set architectures types orthogonal instruction set cisc risc application specific edge trips vliw epic misc oisc nisc zisc visc architecture quantum computing comparison addressing modes instruction sets motorola 68000 series vax pdp 11 x86 arm stanford mips mips mips x power power powerpc power isa clipper architecture sparc superh dec alpha etrax cris m32r unicore itanium openrisc risc v microblaze lmc system 3x0 s 360 s 370 s 390 z architecture tilera isa visc architecture epiphany architecture others execution instruction pipelining pipeline stall operand forwarding classic risc pipeline hazards data dependency structural control false sharing out of order scoreboarding tomasulo algorithm reservation station re order buffer register renaming wide issue speculative branch prediction memory dependence prediction parallelism level bit bit serial word instruction pipelining scalar superscalar task thread process data vector memory distributed multithreading temporal simultaneous hyperthreading speculative preemptive cooperative flynn s taxonomy sisd simd array processing simt pipelined processing associative processing swar misd mimd spmd processor performance transistor count instructions per cycle ipc cycles per instruction cpi instructions per second ips floating point operations per second flops transactions per second tps synaptic updates per second sups performance per watt ppw cache performance metrics computer performance by orders of magnitude types central processing unit cpu graphics processing unit gpu gpgpu vector barrel stream tile processor coprocessor pal asic fpga fpoa cpld multi chip module mcm system in a package sip package on a package pop by application embedded system microprocessor microcontroller mobile notebook ultra low voltage asip soft microprocessor systems on chip system on a chip soc multiprocessor mpsoc programmable psoc network on a chip noc hardware accelerators coprocessor ai accelerator graphics processing unit gpu image processor vision processing unit vpu physics processing unit ppu digital signal processor dsp tensor processing unit tpu secure cryptoprocessor network processor baseband processor word size 1 bit 4 bit 8 bit 12 bit 15 bit 16 bit 24 bit 32 bit 48 bit 64 bit 128 bit 256 bit 512 bit bit slicing others variable core count single core multi core manycore heterogeneous architecture components core cache cpu cache scratchpad memory data cache instruction cache replacement policies coherence bus clock rate clock signal fifo functional units arithmetic logic unit alu address generation unit agu floating point unit fpu memory management unit mmu load store unit translation lookaside buffer tlb branch predictor branch target predictor integrated memory controller imc memory management unit instruction decoder logic combinational sequential glue logic gate quantum array registers processor register status register stack register register file memory buffer memory address register program counter control unit hardwired control unit instruction unit data buffer write buffer microcode rom horizontal microcode counter datapath multiplexer demultiplexer adder multiplier cpu binary decoder address decoder sum addressed decoder barrel shifter circuitry integrated circuit 3d mixed signal power management boolean digital analog quantum switch power management pmu apm acpi dynamic frequency scaling dynamic voltage scaling clock gating performance per watt ppw related history of general purpose cpus microprocessor chronology processor design digital electronics hardware security module semiconductor device fabrication tick tock model pin grid array chip carrier retrieved from https en wikipedia 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