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veral identifying characteristics within a given cpu instructions are issued from a sequential instruction stream the cpu dynamically checks for data dependencies between instructions at run time versus software checking at compile time the cpu can execute multiple instructions per clock cycle contents 1 history 2 scalar to superscalar 3 limitations 4 alternatives 5 see also 6 references 7 external links history edit seymour cray s cdc 6600 from 1964 is often mentioned as the first superscalar design the 1967 ibm system 360 model 91 was another superscalar mainframe the motorola mc88100 1988 the intel i960 ca 1989 and the amd 29000 series 29050 1990 microprocessors were the first commercial single chip superscalar microprocessors risc microprocessors like these were the first to have superscalar execution because risc architectures free transistors and die area which can be used to include multiple execution units this was why risc designs were faster than cisc designs through the 1980s and into the 1990s except for cpus used in low power applications embedded systems and battery powered devices essentially all general purpose cpus developed since about 1998 are superscalar the p5 pentium was the first superscalar x86 processor the nx586 p6 pentium pro and amd k5 were among the first designs which decode x86 instructions asynchronously into dynamic microcode like micro op sequences prior to actual execution on a superscalar microarchitecture this opened up for dynamic scheduling of buffered partial instructions and enabled more parallelism to be extracted compared to the more rigid methods used in the simpler p5 pentium it also simplified speculative execution and allowed higher clock frequencies compared to designs such as the advanced cyrix 6x86 scalar to superscalar edit the simplest processors are scalar processors each instruction executed by a scalar processor typically manipulates one or two data items at a time by contrast each instruction executed by a vector processor operates simultaneously on many data items an analogy is the difference between scalar and vector arithmetic a superscalar processor is a mixture of the two each instruction processes one data item but there are multiple execution units within each cpu thus multiple instructions can be processing separate data items concurrently superscalar cpu design emphasizes improving the instruction dispatcher accuracy and allowing it to keep the multiple execution units in use at all times this has become increasingly important as the number of units has increased while early superscalar cpus would have two alus and a single fpu a later design such as the powerpc 970 includes four alus two fpus and two simd units if the dispatcher is ineffective at keeping all of these units fed with instructions the performance of the system will be no better than that of a simpler cheaper design a superscalar processor usually sustains an execution rate in excess of one instruction per machine cycle but merely processing multiple instructions concurrently does not make an architecture superscalar since pipelined multiprocessor or multi core architectures also achieve that but with different methods in a superscalar cpu the dispatcher reads instructions from memory and decides which ones can be run in parallel dispatching each to one of the several execution units contained inside a single cpu therefore a superscalar processor can be envisioned having multiple parallel pipelines each of which is processing instructions simultaneously from a single instruction thread limitations edit available performance improvement from superscalar techniques is limited by three key areas the degree of intrinsic parallelism in the instruction stream instructions requiring the same computational resources from the cpu the complexity and time cost of dependency checking logic and register renaming circuitry the branch instruction processing existing binary executable programs have varying degrees of intrinsic parallelism in some cases instructions are not dependent on each other and can be executed simultaneously in other cases they are inter dependent one instruction impacts either resources or results of the other the instructions a b c d e f can be run in parallel because none of the results depend on other calculations however the instructions a b c b e f might not be runnable in parallel depending on the order in which the instructions complete while they move through the units although the instruction stream may contain no inter instruction dependencies a superscalar cpu must nonetheless check for that possibility since there is no assurance otherwise and failure to detect a dependency would produce incorrect results no matter how advanced the semiconductor process or how fast the switching speed this places a practical limit on how many instructions can be simultaneously dispatched while process advances will allow ever greater numbers of execution units e g alus the burden of checking instruction dependencies grows rapidly as does the complexity of register renaming circuitry to mitigate some dependencies collectively the power consumption complexity and gate delay costs limit the achievable superscalar speedup however even given infinitely fast dependency checking logic on an otherwise conventional superscalar cpu if the instruction stream itself has many dependencies this would also limit the possible speedup thus the degree of intrinsic parallelism in the code stream forms a second limitation alternatives edit collectively these limits drive investigation into alternative architectural changes such as very long instruction word vliw explicitly parallel instruction computing epic simultaneous multithreading smt and multi core computing with vliw the burdensome task of dependency checking by hardware logic at run time is removed and delegated to the compiler explicitly parallel instruction computing epic is like vliw with extra cache prefetching instructions simultaneous multithreading smt is a technique for improving the overall efficiency of superscalar processors smt permits multiple independent threads of execution to better utilize the resources provided by modern processor architectures superscalar processors differ from multi core processors in that the several execution units are not entire processors a single processor is composed of finer grained execution units such as the alu integer multiplier integer shifter fpu etc there may be multiple versions of each execution unit to enable execution of many instructions in parallel this differs from a multi core processor that concurrently processes instructions from multiple threads one thread per processing unit called core it also differs from a pipelined processor where the multiple instructions can concurrently be in various stages of execution assembly line fashion the various alternative techniques are not mutually exclusive they can be and frequently are combined in a single processor thus a multicore cpu is possible where each core is an independent processor containing multiple parallel pipelines each pipeline being superscalar some processors also include vector capability see also edit eager execution hyper threading simultaneous multithreading out of order execution shelving buffer speculative execution software lockout a multiprocessor issue similar to logic dependencies on superscalars super threading references edit what is a superscalar processor definition from techopedia techopedia com retrieved 2022 08 29 mike johnson superscalar microprocessor design prentice hall 1991 isbn 0 13 875634 1 sorin cotofana stamatis vassiliadis on the design complexity of the issue logic of superscalar machines euromicro 1998 10277 10284 steven mcgeady the i960ca superscalar implementation of the 80960 architecture ieee 1990 pp 232 240 steven mcgeady et al performance enhancements in the superscalar i960mm embedded microprocessor acm proceedings of the 1991 conference on computer architecture compcon 1991 pp 4 7 external links edit eager execution dual path multiple path by mark smotherman v t e processor technologies models abstract machine stored program computer finite state machine with datapath hierarchical deterministic finite automaton queue automaton cellular automaton quantum cellular automaton turing machine alternating turing machine universal post turing quantum nondeterministic turing machine probabilistic turing machine hypercomputation zeno machine belt machine stack machine register machines counter pointer random access random access stored program architecture microarchitecture von neumann harvard modified dataflow transport triggered cellular endianness memory access numa huma load store register memory cache hierarchy memory hierarchy virtual memory secondary storage heterogeneous fabric multiprocessing cognitive neuromorphic instruction set architectures types orthogonal instruction set cisc risc application specific edge trips vliw epic misc oisc nisc zisc visc architecture quantum computing comparison addressing modes instruction sets motorola 68000 series vax pdp 11 x86 arm stanford mips mips mips x power power powerpc power isa clipper architecture sparc superh dec alpha etrax cris m32r unicore itanium openrisc risc v microblaze lmc system 3x0 s 360 s 370 s 390 z architecture tilera isa visc architecture epiphany architecture others execution instruction pipelining pipeline stall operand forwarding classic risc pipeline hazards data dependency structural control false sharing out of order scoreboarding tomasulo algorithm reservation station re order buffer register renaming wide issue speculative branch prediction memory dependence prediction parallelism level bit bit serial word instruction pipelining scalar superscalar task thread process data vector memory distributed multithreading temporal simultaneous hyperthreading speculative preemptive cooperative flynn s taxonomy sisd simd array processing simt pipelined processing associative processing swar misd mimd spmd processor performance transistor count instructions per cycle ipc cycles per instruction cpi instructions per second ips floating point operations per second flops transactions per second tps synaptic updates per second sups performance per watt ppw cache performance metrics computer performance by orders of magnitude types central processing unit cpu graphics processing unit gpu gpgpu vector barrel stream tile processor coprocessor pal asic fpga fpoa cpld multi chip module mcm system in a package sip package on a package pop by application embedded system microprocessor microcontroller mobile notebook ultra low voltage asip soft microprocessor systems on chip system on a chip soc multiprocessor mpsoc programmable psoc network on a chip noc hardware accelerators coprocessor ai accelerator graphics processing unit gpu image processor vision processing unit vpu physics processing unit ppu digital signal processor dsp tensor processing unit tpu secure cryptoprocessor network processor baseband processor word size 1 bit 4 bit 8 bit 12 bit 15 bit 16 bit 24 bit 32 bit 48 bit 64 bit 128 bit 256 bit 512 bit bit slicing others variable core count single core multi core manycore heterogeneous architecture components core cache cpu cache scratchpad memory data cache instruction cache replacement policies coherence bus clock rate clock signal fifo functional units arithmetic logic unit alu address generation unit agu floating point unit fpu memory management unit mmu load store unit translation lookaside buffer tlb branch predictor branch target predictor integrated memory controller imc memory management unit instruction decoder logic combinational sequential glue logic gate quantum array registers processor register status register stack register register file memory buffer memory address register program counter control unit hardwired control unit instruction unit data buffer write buffer microcode rom horizontal microcode counter datapath multiplexer demultiplexer adder multiplier cpu binary decoder address decoder sum addressed decoder barrel shifter circuitry integrated circuit 3d mixed signal power management boolean digital analog quantum switch power management pmu apm acpi dynamic frequency scaling dynamic voltage scaling clock gating performance per watt ppw related history of general purpose cpus microprocessor chronology processor design digital electronics hardware security module semiconductor device fabrication tick tock model pin grid array chip carrier v t e parallel computing general distributed computing parallel computing massively parallel cloud computing high performance computing multiprocessing manycore processor gpgpu computer network systolic array levels bit instruction thread task data memory loop pipeline multithreading temporal simultaneous smt speculative spmt preemptive cooperative clustered multi thread cmt hardware scout theory pram model pem model analysis of parallel algorithms amdahl s law gustafson s law cost efficiency karp flatt metric slowdown speedup elements process thread fiber instruction window array coordination multiprocessing memory coherence cache coherence cache invalidation barrier synchronization application checkpointing programming stream processing dataflow programming models implicit parallelism explicit parallelism concurrency non blocking algorithm hardware flynn s taxonomy sisd simd array processing simt pipelined processing associative processing misd mimd dataflow architecture pipelined processor superscalar processor vector processor multiprocessor symmetric asymmetric memory shared distributed distributed shared uma numa coma massively parallel computer computer cluster beowulf cluster grid computer hardware acceleration apis ateji px boost chapel hpx charm cilk coarray fortran cuda dryad c amp global arrays gpuopen mpi openmp opencl openhmpp openacc parallel extensions pvm pthreads raftlib rocm upc tbb zpl problems automatic parallelization deadlock deterministic algorithm embarrassingly parallel parallel slowdown race condition software lockout scalability starvation category parallel computing retrieved from https en wikipedia org w index php title superscalar_processor oldid 1107661073 categories superscalar microprocessors classes of computers computer architecture parallel computing hidden categories articles with short description short description matches wikidata articles lacking in text citations from october 2017 all articles lacking in text citations navigation menu personal tools not logged in talk contributions create account log in namespaces article talk english views read edit view history more search navigation main page contents current events random article about wikipedia contact us donate contribute help learn to edit community portal recent changes upload file tools what links here related changes upload file special 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