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Text of the page (random words):
the byte within the word and the word address of the data instructions could automatically adjust the pointer to the next byte on for example load and deposit store operations powers of two edit different amounts of memory are used to store data values with different degrees of precision the commonly used sizes are usually a power of two multiple of the unit of address resolution byte or word converting the index of an item in an array into the memory address offset of the item then requires only a shift operation rather than a multiplication in some cases this relationship can also avoid the use of division operations as a result most modern computer designs have word sizes and other operand sizes that are a power of two times the size of a byte size families edit as computer designs have grown more complex the central importance of a single word size to an architecture has decreased although more capable hardware can use a wider variety of sizes of data market forces exert pressure to maintain backward compatibility while extending processor capability as a result what might have been the central word size in a fresh design has to coexist as an alternative size to the original word size in a backward compatible design the original word size remains available in future designs forming the basis of a size family in the mid 1970s dec designed the vax to be a 32 bit successor of the 16 bit pdp 11 they used word for a 16 bit quantity while longword referred to a 32 bit quantity this terminology is the same as the terminology used for the pdp 11 this was in contrast to earlier machines where the natural unit of addressing memory would be called a word while a quantity that is one half a word would be called a halfword in fitting with this scheme a vax quadword is 64 bits they continued this 16 bit word 32 bit longword 64 bit quadword terminology with the 64 bit alpha another example is the x86 family of which processors of three different word lengths 16 bit later 32 and 64 bit have been released while word continues to designate a 16 bit quantity as software is routinely ported from one word length to the next some apis and documentation define or refer to an older and thus shorter word length than the full word length on the cpu that software may be compiled for also similar to how bytes are used for small numbers in many programs a shorter word 16 or 32 bits may be used in contexts where the range of a wider word is not needed especially where this can save considerable stack space or cache memory space for example microsoft s windows api maintains the programming language definition of word as 16 bits despite the fact that the api may be used on a 32 or 64 bit x86 processor where the standard word size would be 32 or 64 bits respectively data structures containing such different sized words refer to them as word 16 bits 2 bytes dword 32 bits 4 bytes qword 64 bits 8 bytes a similar phenomenon has developed in intel s x86 assembly language because of the support for various sizes and backward compatibility in the instruction set some instruction mnemonics carry d or q identifiers denoting double quad or double quad which are in terms of the architecture s original 16 bit word size an example with a different word size is the ibm system 360 family in the system 360 architecture system 370 architecture and system 390 architecture there are 8 bit byte s 16 bit halfword s 32 bit word s and 64 bit doubleword s the z architecture which is the 64 bit member of that architecture family continues to refer to 16 bit halfword s 32 bit word s and 64 bit doubleword s and additionally features 128 bit quadword s in general new processors must use the same data word lengths and virtual address widths as an older processor to have binary compatibility with that older processor often carefully written source code written with source code compatibility and software portability in mind can be recompiled to run on a variety of processors even ones with different data word lengths or different address widths or both table of word sizes edit key bit bits c characters d decimal digits w word size of architecture n variable size wm word mark year computer architecture word size w integer sizes floating point sizes instruction sizes unit of address resolution char size 1837 babbage analytical engine 50 d w five different cards were used for different functions exact size of cards not known w 1941 zuse z3 22 bit w 8 bit w 1942 abc 50 bit w 1944 harvard mark i 23 d w 24 bit 1946 1948 1953 eniac w panel 16 5 w panel 26 6 10 d w 2 w w w 2 d 4 d 6 d 8 d 2 d 4 d 6 d 8 d w 1948 manchester baby 32 bit w w w 1951 univac i 12 d w 1 2 w w 1 d 1952 ias machine 40 bit w 1 2 w w 5 bit 1952 fast universal digital computer m 2 34 bit w w 34 bit 4 bit opcode plus 3 10 bit address 10 bit 1952 ibm 701 36 bit 1 2 w w 1 2 w 1 2 w w 6 bit 1952 univac 60 n d 1 d 10 d 2 d 3 d 1952 arra i 30 bit w w w 5 bit 1953 ibm 702 n c 0 c 511 c 5 c c 6 bit 1953 univac 120 n d 1 d 10 d 2 d 3 d 1953 arra ii 30 bit w 2 w 1 2 w w 5 bit 1954 1955 ibm 650 w ibm 653 10 d w w w w 2 d 1954 ibm 704 36 bit w w w w 6 bit 1954 ibm 705 n c 0 c 255 c 5 c c 6 bit 1954 ibm norc 16 d w w 2 w w w 1956 ibm 305 n d 1 d 100 d 10 d d 1 d 1956 armac 34 bit w w 1 2 w w 5 bit 6 bit 1956 lgp 30 31 bit w 16 bit w 6 bit 1957 autonetics recomp i 40 bit w 79 bit 8 d 15 d 1 2 w 1 2 w w 5 bit 1958 univac ii 12 d w 1 2 w w 1 d 1958 sage 32 bit 1 2 w w w 6 bit 1958 autonetics recomp ii 40 bit w 79 bit 8 d 15 d 2 w 1 2 w 1 2 w w 5 bit 1958 setun 6 trit 9 5 bits b up to 6 tryte up to 3 trytes 4 trit 1958 electrologica x1 27 bit w 2 w w w 5 bit 6 bit 1959 ibm 1401 n c 1 c 1 c 2 c 4 c 5 c 7 c 8 c c 6 bit wm 1959 tbd ibm 1620 n d 2 d 4 d 102 d 12 d d 2 d 1960 larc 12 d w 2 w w 2 w w w 2 d 1960 cdc 1604 48 bit w w 1 2 w w 6 bit 1960 ibm 1410 n c 1 c 1 c 2 c 6 c 7 c 11 c 12 c c 6 bit wm 1960 ibm 7070 10 d c w 1 9 d w w w d 2 d 1960 pdp 1 18 bit w w w 6 bit 1960 elliott 803 39 bit 1961 ibm 7030 stretch 64 bit 1 bit 64 bit 1 d 16 d w 1 2 w w bit integer 1 2 w branch w float 1 bit 8 bit 1961 ibm 7080 n c 0 c 255 c 5 c c 6 bit 1962 ge 6xx 36 bit w 2 w w 2 w 80 bit w w 6 bit 9 bit 1962 univac iii 25 bit w 2 w 3 w 4 w 6 d 12 d w w 6 bit 1962 autonetics d 17b minuteman i guidance computer 27 bit 11 bit 24 bit 24 bit w 1962 univac 1107 36 bit 1 6 w 1 3 w 1 2 w w w w w 6 bit 1962 ibm 7010 n c 1 c 1 c 2 c 6 c 7 c 11 c 12 c c 6 b wm 1962 ibm 7094 36 bit w w 2 w w w 6 bit 1962 sds 9 series 24 bit w 2 w w w 1963 1966 apollo guidance computer 15 bit w w 2 w w 1963 saturn launch vehicle digital computer 26 bit w 13 bit w 1964 1966 pdp 6 pdp 10 36 bit w w 2 w w w 6 bit 7 bit typical 9 bit 1964 titan 48 bit w w w w w 1964 cdc 6600 60 bit w w 1 4 w 1 2 w w 6 bit 1964 autonetics d 37c minuteman ii guidance computer 27 bit 11 bit 24 bit 24 bit w 4 bit 5 bit 1965 gemini guidance computer 39 bit 26 bit 13 bit 13 bit 26 bit 1965 ibm 1130 16 bit w 2w 2w 3w w 2w w 8 bit 1965 ibm system 360 32 bit 1 2 w w 1 d 16 d w 2 w 1 2 w w 1 1 2 w 8 bit 8 bit 1965 univac 1108 36 bit 1 6 w 1 4 w 1 3 w 1 2 w w 2 w w 2 w w w 6 bit 9 bit 1965 pdp 8 12 bit w w w 8 bit 1965 electrologica x8 27 bit w 2 w w w 6 bit 7 bit 1966 sds sigma 7 32 bit 1 2 w w w 2 w w 8 bit 8 bit 1969 four phase systems al1 8 bit w 1970 mp944 20 bit w 1970 pdp 11 16 bit w 2 w 4 w w 2 w 3 w 8 bit 8 bit 1971 cdc star 100 64 bit 1 2 w w 1 2 w w 1 2 w w bit 8 bit 1971 tms1802nc 4 bit w 1971 intel 4004 4 bit w d 2 w 4 w w 1972 intel 8008 8 bit w 2 d w 2 w 3 w w 8 bit 1972 calcomp 900 9 bit w w 2 w w 8 bit 1974 intel 8080 8 bit w 2 w 2 d w 2 w 3 w w 8 bit 1975 illiac iv 64 bit w w 1 2 w w w 1975 motorola 6800 8 bit w 2 d w 2 w 3 w w 8 bit 1975 mos tech 6501 mos tech 6502 8 bit w 2 d w 2 w 3 w w 8 bit 1976 cray 1 64 bit 24 bit w w 1 4 w 1 2 w w 8 bit 1976 zilog z80 8 bit w 2 w 2 d w 2 w 3 w 4 w 5 w w 8 bit 1978 1980 16 bit x86 intel 8086 w floating point intel 8087 16 bit 1 2 w w 2 d 2 w 4 w 5 w 17 d 1 2 w w 7 w 8 bit 8 bit 1978 vax 32 bit 1 4 w 1 2 w w 1 d 31 d 1 bit 32 bit w 2 w 1 4 w 14 1 4 w 8 bit 8 bit 1979 1984 motorola 68000 series w floating point 32 bit 1 4 w 1 2 w w 2 d w 2 w 2 1 2 w 1 2 w w 7 1 2 w 8 bit 8 bit 1985 ia 32 intel 80386 w floating point 32 bit 1 4 w 1 2 w w w 2 w 80 bit 8 bit 120 bit 1 4 w 3 3 4 w 8 bit 8 bit 1985 armv1 32 bit 1 4 w w w 8 bit 8 bit 1985 mips i 32 bit 1 4 w 1 2 w w w 2 w w 8 bit 8 bit 1991 cray c90 64 bit 32 bit w w 1 4 w 1 2 w 48 bit w 8 bit 1992 alpha 64 bit 8 bit 1 4 w 1 2 w w 1 2 w w 1 2 w 8 bit 8 bit 1992 powerpc 32 bit 1 4 w 1 2 w w w 2 w w 8 bit 8 bit 1996 armv4 w thumb 32 bit 1 4 w 1 2 w w w 1 2 w w 8 bit 8 bit 2000 ibm z architecture w vector facility 64 bit 1 4 w 1 2 w w 1 d 31 d 1 2 w w 2 w 1 4 w 1 2 w 3 4 w 8 bit 8 bit utf 16 utf 32 2001 ia 64 64 bit 8 bit 1 4 w 1 2 w w 1 2 w w 41 bit in 128 bit bundles 7 8 bit 8 bit 2001 armv6 w vfp 32 bit 8 bit 1 2 w w w 2w 1 2 w w 8 bit 8 bit 2003 x86 64 64 bit 8 bit 1 4 w 1 2 w w 1 2 w w 80 bit 8 bit 120 bit 8 bit 8 bit 2013 armv8 a and armv9 a 64 bit 8 bit 1 4 w 1 2 w w 1 2 w w 1 2 w 8 bit 8 bit year computer architecture word size w integer sizes floating point sizes instruction sizes unit of address resolution char size key bit bits d decimal digits w word size of architecture n variable size 8 9 see also edit integer computer science notes edit many early computers were decimal and a few were ternary the bit equivalent is computed by taking the amount of information entropy provided by the trit which is log 2 3 displaystyle log _ 2 3 this gives an equivalent of about 9 51 bits for 6 trits three state sign references edit a b beebe nelson h f 2017 08 22 chapter i integer arithmetic the mathematical function computation handbook programming using the mathcw portable software library 1 ed salt lake city ut usa springer international publishing ag p 970 doi 10 1007 978 3 319 64110 2 isbn 978 3 319 64109 6 lccn 2017947446 s2cid 30244721 dreyfus phillippe 1958 05 08 1958 05 06 written at los angeles california usa system design of the gamma 60 pdf western joint computer conference contrasts in computers acm new york ny usa pp 130 133 ire acm aiee 58 western archived pdf from the original on 2017 04 03 retrieved 2017 04 03 internal data code is used quantitative numerical data are coded in a 4 bit decimal code qualitative alpha numerical data are coded in a 6 bit alphanumerical code the internal instruction code means that the instructions are coded in straight binary code as to the internal information length the information quantum is called a catena and it is composed of 24 bits representing either 6 decimal digits or 4 alphanumerical characters this quantum must contain a multiple of 4 and 6 bits to represent a whole number of decimal or alphanumeric characters twenty four bits was found to be a good compromise between the minimum 12 bits which would lead to a too low transfer flow from a parallel readout core memory and 36 bits or more which was judged as too large an information quantum the catena is to be considered as the equivalent of a character in variable word length machines but it cannot be called so as it may contain several characters it is transferred in series to and from the main memory not wanting to call a quantum a word or a set of characters a letter a word is a word and a quantum is something else a new word was made and it was called a catena it is an english word and exists in webster s although it does not in french webster s definition of the word catena is a connected series therefore a 24 bit information item the word catena will be used hereafter the internal code therefore has been defined now what are the external data codes these depend primarily upon the information handling device involved the gamma 60 fr is designed to handle information relevant to any binary coded structure thus an 80 column punched card is considered as a 960 bit information item 12 rows multiplied by 80 columns equals 960 possible punches is stored as an exact image in 960 magnetic cores of the main memory with 2 card columns occupying one catena blaauw gerrit anne brooks jr frederick phillips buchholz werner 1962 4 natural data units pdf in buchholz werner ed planning a computer system project stretch mcgraw hill book company inc the maple press company york pa pp 39 40 lccn 61 10466 archived pdf from the original on 2017 04 03 retrieved 2017 04 03 terms used here to describe the structure imposed by the machine design in addition to bit are listed below byte denotes a group of bits used to encode a character or the number of bits transmitted in parallel to and from input output units a term other than character is used here because a given character may be represented in different applications by more than one code and different codes may use different numbers of bits i e different byte sizes in input output transmission the grouping of bits may be completely arbitrary and have no relation to actual characters the term is coined from bite but respelled to avoid accidental mutation to bit a word consists of the number of data bits transmitted in parallel from or to memory in one memory cycle word size is thus defined as a structural property of the memory the term catena was coined for this purpose by the designers of the bull gamma 60 fr computer block refers to the number of words transmitted to or from an input output unit in response to a single input output instruction block size is a structural property of an input output unit it may have been fixed by the design or left to be varied by the program format pdf reference manual 7030 data processing system pdf ibm august 1961 pp 50 57 retrieved 2021 12 15 clippinger richard f 1948 09 29 a logical coding system applied to the eniac electronic numerical integrator and computer aberdeen proving ground maryland us ballistic research laboratories report no 673 project no tb3 0007 of the research and development division ordnance department retrieved 2017 04 05 cite web cs1 maint url status link clippinger richard f 1948 09 29 a logical coding system applied to the eniac aberdeen proving ground maryland us ballistic research laboratories section viii modified eniac retrieved 2017 04 05 cite web cs1 maint url status link 4 instruction formats pdf intel itanium architecture software developer s manual vol 3 intel itanium instruction set reference p 3 293 retrieved 2022 04 25 three instructions are grouped together into 128 bit sized and aligned containers called bundles each bundle contains three 41 bit instruction slots and a 5 bit template field blaauw gerrit anne brooks jr frederick phillips 1997 computer architecture concepts and evolution 1 ed addison wesley isbn 0 201 10557 8 1213 pages nb this is a single volume edition this work was also available in a two volume version ralston anthony reilly edwin d 1993 encyclopedia of computer science 3rd ed van nostrand reinhold isbn 0 442 27679 6 v t e units of information platform independent units bit ...
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