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Text of the page (random words):
y edit this section needs expansion you can help by adding to it january 2015 see also list of silicon producers in the semiconductor or silicon wafer industry the term wafer appeared in the 1950s to describe a thin round slice of semiconductor material typically germanium or silicon round shape comes from single crystal ingots usually produced using the czochralski method silicon wafers were first introduced in the 1940s 2 3 by 1960 silicon wafers were being manufactured in the u s by companies such as memc sunedison in 1965 american engineers eric o ernst donald j hurd and gerard seeley while working under ibm filed patent us3423629a 4 for the first high capacity epitaxial apparatus silicon wafers are made by companies such as sumco shin etsu chemical 5 hemlock semiconductor corporation and siltronic production edit formation edit see also boule crystal the czochralski method wafers are formed of highly pure 6 nearly defect free single crystalline material with a purity of 99 9999999 9n or higher 6 one process for forming crystalline wafers is known as the czochralski method invented by polish chemist jan czochralski in this process a cylindrical ingot of high purity monocrystalline semiconductor such as silicon or germanium called a boule is formed by pulling a seed crystal from a melt 7 8 donor impurity atoms such as boron or phosphorus in the case of silicon can be added to the molten intrinsic material in precise amounts in order to dope the crystal thus changing it into an extrinsic semiconductor of n type or p type the boule is then sliced with a wafer saw a type of wire saw machined to improve flatness chemically etched to remove crystal damage from machining steps and finally polished to form wafers 9 the size of wafers for photovoltaics is 100 200 mm square and the thickness is 100 500 μm 10 electronics use wafer sizes from 100 to 450 mm diameter the largest wafers made have a diameter of 450 mm 11 but are not yet in general use cleaning texturing and etching edit wafers are cleaned with weak acids to remove unwanted particles there are several standard cleaning procedures to make sure the surface of a silicon wafer contains no contamination one of the most effective methods is rca clean when used for solar cells the wafers are textured to create a rough surface to increase surface area and so their efficiency the generated psg phosphosilicate glass is removed from the edge of the wafer in the etching 12 wafer properties edit standard wafer sizes edit silicon edit silicon wafers are available in a variety of diameters from 25 4 mm 1 inch to 300 mm 11 8 inches 13 14 semiconductor fabrication plants colloquially known as fabs are defined by the diameter of wafers that they are tooled to produce the diameter has gradually increased to improve throughput and reduce cost with the current state of the art fab using 300 mm with a proposal to adopt 450 mm 15 16 intel tsmc and samsung were separately conducting research to the advent of 450 mm prototype research fabs though serious hurdles remain 17 2 inch 51 mm 4 inch 100 mm 6 inch 150 mm and 8 inch 200 mm wafers wafer size typical thickness year introduced 13 weight per wafer 100 mm2 10 mm die per wafer 1 inch 25 mm 1960 2 inch 51 mm 275 μm 1969 9 3 inch 76 mm 375 μm 1972 29 4 inch 100 mm 525 μm 1976 10 grams 18 56 4 9 inch 125 mm 625 μm 1981 95 150 mm 5 9 inch usually referred to as 6 inch 675 μm 1983 144 200 mm 7 9 inch usually referred to as 8 inch 725 μm 1992 53 grams 18 269 300 mm 11 8 inch usually referred to as 12 inch 775 μm 2002 125 grams 18 640 450 mm 17 7 inch proposed 19 925 μm 342 grams 18 1490 675 millimetre 26 6 in theoretical 20 unknown unknown 3427 wafers grown using materials other than silicon will have different thicknesses than a silicon wafer of the same diameter wafer thickness is determined by the mechanical strength of the material used the wafer must be thick enough to support its own weight without cracking during handling the tabulated thicknesses relate to when that process was introduced and are not necessarily correct currently for example the ibm bicmos7wl process is on 8 inch wafers but these are only 200 μm thick the weight of the wafer goes up along with its thickness and diameter citation needed historical increases of wafer size edit a unit of wafer fabrication step such as an etch step can produce more chips proportional to the increase in wafer area while the cost of the unit fabrication step goes up more slowly than the wafer area this was the cost basis for increasing wafer size conversion to 300 mm wafers from 200 mm wafers began in early 2000 and reduced the price per die for about 30 40 21 larger diameter wafers allow for more die per wafer photovoltaic edit this section needs expansion you can help by adding to it july 2020 m1 wafer size 156 75 mm is in the process of being phased out in china as of 2020 various nonstandard wafer sizes have arisen so efforts to fully adopt the m10 standard 182 mm are ongoing like other semiconductor fabrication processes driving down costs has been the main driving factor for this attempted size increase in spite of the differences in the manufacturing processes of different types of devices citation needed crystalline orientation edit diamond cubic crystal structure of a silicon unit cell flats can be used to denote doping and crystallographic orientation red represents material that has been removed wafers are grown from crystal having a regular crystal structure with silicon having a diamond cubic structure with a lattice spacing of 5 430710 å 0 5430710 nm 22 when cut into wafers the surface is aligned in one of several relative directions known as crystal orientations orientation is defined by the miller index with 100 or 111 faces being the most common for silicon 22 orientation is important since many of a single crystal s structural and electronic properties are highly anisotropic ion implantation depths depend on the wafer s crystal orientation since each direction offers distinct paths for transport 23 wafer cleavage typically occurs only in a few well defined directions scoring the wafer along cleavage planes allows it to be easily diced into individual chips dies so that the billions of individual circuit elements on an average wafer can be separated into many individual circuits citation needed crystallographic orientation notches edit wafers under 200 mm diameter have flats cut into one or more sides indicating the crystallographic planes of the wafer usually a 110 face in earlier generation wafers a pair of flats at different angles additionally conveyed the doping type see illustration for conventions wafers of 200 mm diameter and above use a single small notch to convey wafer orientation with no visual indication of doping type 450 mm wafers are notchless relying on a laser scribed structure on the wafer surface for orientation 24 impurity doping edit silicon wafers are generally not 100 pure silicon but are instead formed with an initial impurity doping concentration between 10 13 and 10 16 atoms per cm 3 of boron phosphorus arsenic or antimony which is added to the melt and defines the wafer as either bulk n type or p type 25 however compared with single crystal silicon s atomic density of 5 10 22 atoms per cm 3 this still gives a purity greater than 99 9999 the wafers can also be initially provided with some interstitial oxygen concentration carbon and metallic contamination are kept to a minimum 26 transition metals in particular must be kept below parts per billion concentrations for electronic applications 27 450 mm wafers edit challenges edit there is considerable resistance to the 450 mm transition despite the possible productivity improvement because of concern about insufficient return on investment 21 there are also issues related to increased inter die edge to edge wafer variation and additional edge defects 450mm wafers are expected to cost 4 times as much as 300mm wafers and equipment costs are expected to rise by 20 to 50 28 higher cost semiconductor fabrication equipment for larger wafers increases the cost of 450 mm fabs semiconductor fabrication facilities or factories lithographer chris mack claimed in 2012 that the overall price per die for 450 mm wafers would be reduced by only 10 20 compared to 300 mm wafers because over 50 of total wafer processing costs are lithography related converting to larger 450 mm wafers would reduce price per die only for process operations such as etch where cost is related to wafer count not wafer area citation needed cost for processes such as lithography is proportional to wafer area and larger wafers would not reduce the lithography contribution to die cost 29 nikon planned to deliver 450 mm lithography equipment in 2015 with volume production in 2017 30 31 in november 2013 asml paused development of 450 mm lithography equipment citing uncertain timing of chipmaker demand 32 in 2012 a group consisting of new york state suny poly college of nanoscale science and engineering cnse intel tsmc samsung ibm globalfoundries and nikon companies has formed a public private partnership called global 450mm consortium g450c similar to sematech who made a 5 year plan expiring in 2016 to develop a cost effective wafer fabrication infrastructure equipment prototypes and tools to enable coordinated industry transition to 450mm wafer level 33 34 in the mid of 2014 cnse has announced that it will reveal first fully patterned 450mm wafers at semicon west 35 in early 2017 the g450c began to dismantle its activities over 450mm wafer research due to undisclosed reasons 36 37 38 various sources have speculated that demise of the group came after charges of bid rigging made against alain e kaloyeros who at the time was a chief executive at the suny poly 38 37 39 the industry realization of the fact that the 300mm manufacturing optimization is more cheap than costly 450mm transition may also have played a role 38 the timeline for 450 mm has not been fixed in 2012 it was expected that 450mm production would start in 2017 which never realized 40 41 mark durcan then ceo of micron technology said in february 2014 that he expects 450 mm adoption to be delayed indefinitely or discontinued i am not convinced that 450mm will ever happen but to the extent that it does it s a long way out in the future there is not a lot of necessity for micron at least over the next five years to be spending a lot of money on 450mm 42 there is a lot of investment that needs to go on in the equipment community to make that happen and the value at the end of the day so that customers would buy that equipment i think is dubious 43 as of march 2014 intel corporation expected 450 mm deployment by 2020 by the end of this decade 44 mark lapedus of semiengineering com reported in mid 2014 that chipmakers had delayed adoption of 450 mm for the foreseeable future according to this report some observers expected 2018 to 2020 while g dan hutcheson chief executive of vlsi research didn t see 450mm fabs moving into production until 2020 to 2025 45 the step up to 300 mm required major changes with fully automated factories using 300 mm wafers versus barely automated factories for the 200 mm wafers partly because a foup for 300 mm wafers weighs about 7 5 kilograms 46 when loaded with 25 300 mm wafers where a smif weighs about 4 8 kilograms 47 48 18 when loaded with 25 200 mm wafers thus requiring twice the amount of physical strength from factory workers and increasing fatigue 300mm foups have handles so that they can be still be moved by hand 450mm foups weigh 45 kilograms 49 when loaded with 25 450 mm wafers thus cranes are necessary to manually handle the foups 50 and handles are no longer present in the foup foups are moved around using material handling systems from muratec or daifuku these major investments were undertaken in the economic downturn following the dot com bubble resulting in huge resistance to upgrading to 450 mm by the original timeframe on the ramp up to 450 mm the crystal ingots will be 3 times heavier total weight a metric ton and take 2 4 times longer to cool and the process time will be double 51 all told the development of 450 mm wafers requires significant engineering time and cost to overcome analytical die count estimation edit in order to minimize the cost per die manufacturers wish to maximize the number of dies that can be made from a single wafer dies always have a square or rectangular shape due to the constraint of wafer dicing in general this is a computationally complex problem with no analytical solution dependent on both the area of the dies as well as their aspect ratio square or rectangular and other considerations such as the width of the scribeline or saw lane and additional space occupied by alignment and test structures note that gross dpw formulas account only for wafer area that is lost because it cannot be used to make physically complete dies gross dpw calculations do not account for yield loss due to defects or parametric issues citation needed wafermap showing fully patterned dies and partially patterned dies which don t fully lie within the wafer nevertheless the number of gross die per wafer dpw can be estimated starting with the first order approximation or floor function of wafer to die area ratio d p w π r 2 s π d 2 4 s displaystyle dpw left lfloor frac pi r 2 s right rfloor left lfloor frac pi d 2 4s right rfloor where d displaystyle d is the wafer diameter typically in mm s displaystyle s the size of each die mm 2 including the width of the scribeline or in the case of a saw lane the kerf plus a tolerance this formula simply states that the number of dies which can fit on the wafer cannot exceed the area of the wafer divided by the area of each individual die it will always overestimate the true best case gross dpw since it includes the area of partially patterned dies which do not fully lie on the wafer surface see figure these partially patterned dies don t represent complete ics so they cannot be sold as functional parts citation needed refinements of this simple formula typically add an edge correction to account for partial dies on the edge which in general will be more significant when the area of the die is large compared to the total area of the wafer in the other limiting case infinitesimally small dies or infinitely large wafers the edge correction is negligible citation needed the correction factor or correction term generally takes one of the forms cited by de vries 52 d p w π d 2 4 s π d 2 s displaystyle dpw frac displaystyle pi d 2 4s frac displaystyle pi d sqrt 2s area ratio circumference die diagonal length or d p w π d 2 4 s exp 2 s d displaystyle dpw left frac displaystyle pi d 2 4s right exp 2 sqrt s d area ratio scaled by an exponential factor or d p w π d 2 4 s 1 2 s d 2 displaystyle dpw frac displaystyle pi d 2 4s left 1 frac displaystyle 2 sqrt s d right 2 area ratio scaled by a polynomial factor ...