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ipedia 81 captures 13 sep 2006 08 sep 2026 nov dec jan 11 2021 2022 2023 success fail about this capture timestamps the wayback machine http web archive org web 20221211185418 https en wikipedia org wiki power1 power1 from wikipedia the free encyclopedia jump to navigation jump to search multi chip cpu by ibm implementing the power instruction set architecture this article includes a list of general references but it lacks sufficient corresponding inline citations please help to improve this article by introducing more precise citations september 2017 learn how and when to remove this template message power1 general information launched 1990 designed by ibm architecture and classification instruction set power isa history successor power2 power powerpc and power isa architectures nxp formerly freescale and motorola powerpc e series 2006 e200 e300 e500 e600 e5500 e6500 qor series 2008 qoriq qorivva ibm power series 1990 power1 power2 power3 power4 power5 power6 power7 power8 power9 power10 powerpc series 1992 6xx 4xx 7xx 74xx 970 a2 2010 a2i a2o rad series 1997 rad6000 rad750 rad5500 rs64 series 1996 ibm nintendo gekko broadway espresso other titan pwrficient cell xenon x704 related links openpower foundation aim alliance risc blue gene power org papr prep chrp altivec cancelled in gray historic in italic v t e the power1 is a multi chip cpu developed and fabricated by ibm that implemented the power instruction set architecture isa it was originally known as the risc system 6000 cpu or when in an abbreviated form the rs 6000 cpu before introduction of successors required the original name to be replaced with one that used the same naming scheme power n as its successors in order to differentiate it from the newer designs contents 1 history 2 microarchitecture 3 physical description 3 1 chips 3 1 1 instruction cache unit icu 3 1 2 fixed point unit fxu 3 1 3 floating point unit fpu 3 1 4 data cache unit dcu 3 1 5 storage control unit scu 3 1 6 i o unit 4 see also 5 references 6 further reading history edit the power1 was introduced in 1990 with the introduction of the ibm rs 6000 powerserver servers and powerstation workstations which featured the power1 clocked at 20 25 or 30 mhz the power1 received two upgrades one in 1991 with the introduction of the power1 and in 1992 with the introduction of power1 these upgraded versions were clocked higher than the original power1 made possible by improved semiconductor processes the power1 was clocked slightly higher than the original power1 at frequencies of 25 33 and 41 mhz while the power1 took the microarchitecture to its highest frequencies 25 33 41 6 45 50 and 62 5 mhz in september 1993 the power1 and its variants was succeeded by the power2 known briefly as the rios2 an evolution of the power1 microarchitecture the direct derivatives of the power1 are the risc single chip rsc feature reduced single chip variant for entry level rs 6000 systems and the rad6000 a radiation hardened variant of the rsc for space applications an indirect derivative of the power1 is the powerpc 601 a feature reduced variant of the rsc intended for consumer applications the power1 is notable as it represented a number of firsts for ibm and computing in general it was ibm s first risc processor intended for high end applications the romp was considered a commercial failure and was not used in high end workstations it was the first to implement the then new power instruction set architecture and it was ibm s first successful risc processor for computing firsts the power1 would be known for being the first cpu to implement some form of register renaming and out of order execution a technique that improves the performance of superscalar processors but was previously reserved for mainframes the power1 was also the origin for the highly successful families of power powerpc and power isa processors that followed it measuring in hundreds of different implementations the open source gcc compiler removed support for power1 rios and power2 rios2 in the 4 5 release 1 microarchitecture edit the power1 is a 32 bit two way superscalar cpu it contains three major execution units a fixed point unit fxu a branch unit bpu and a floating point unit fpu although the power1 is a 32 bit cpu with a 32 bit physical address its virtual address is 52 bits long the larger virtual address space was chosen because it was beneficial for the performance of applications allowing each one to have a large 4 gb address range the power1 is a big endian cpu that uses a harvard style cache hierarchy with separate instruction and data caches the instruction cache referred to as the i cache by ibm is 8 kb in size and is two way set associative with a line size of 64 bytes the i cache is located on the icu chip the data cache referred to as the d cache by ibm is 32 kb in size for rios 9 configurations and 64 kb in size for rios 1 configurations the d cache is four way set associative with a line size of 128 bytes the d cache employs a store back scheme where data that is to be stored is written to the cache instead of the memory in order to reduce the number of writes destined for the memory the store back scheme is used to prevent the cpu from monopolizing access to the memory although the power1 was a high end design it was not capable of multiprocessing and as such was disadvantaged as the only way performance could be improved was by clocking the cpu higher which was difficult to do with such a large multi chip design ibm used clustering to overcome this disadvantage in power1 systems allowing them to effectively function as if they were multiprocessing systems a concept proven by the popularity of sp1 supercomputers based on the power1 as the power1 was the basis of the power2 and p2sc microprocessors the lack of multiprocessing was passed on to these later power processors multiprocessing was not supported until the introduction of the power3 in 1998 physical description edit a power cpu from an entry level desktop rs 6000 32h workstation the chip complex of the rios 1 processor each line represents a 32 bit bus the chip complex of the rios 9 processor each line represents a 32 bit bus the power1 is a multi chip cpu built from separate chips that are connected to each other by buses the power1 consists of an instruction cache unit icu a fixed point unit fxu a floating point unit fpu a number of data cache units dcu a storage control unit scu and an i o unit due to its modular design ibm was able to create two configurations by simply varying the number of dcus rios 1 and a rios 9 the rios 1 configuration has four dcus the intended amount and was clocked at up to 40 mhz whereas the rios 9 cpu had two dcus and was clocked at lower frequencies the chips are mounted on the cpu planar a printed circuit board pcb using through hole technology due to the large number of chips with wide buses the pcb has eight planes for routing wires four for power and ground and four for signals there are two signal planes on each side of the board while the four power and ground planes are in the center the chips that make up the power1 are fabricated in a 1 0 µm cmos process with three layers of interconnect the chips are packaged in ceramic pin grid array cpga packages that can have up to 300 pins and dissipate a maximum of 4 w of heat each the total number of transistors featured by the power1 assuming that it is a rios 1 configuration is 6 9 million with 2 04 million used for logic and 4 86 million used for memory the die area of all the chips combined is 1 284 mm² the total number of signal pins is 1 464 chips edit instruction cache unit icu edit the icu contains the instruction cache referred to as the i cache by ibm and the branch processing unit bpu the bpu contains the program counter the condition code register and a loop register the icu contains 0 75 million transistors with 0 2 million used for logic and 0 55 million used for sram the icu die measures approximately 160 mm² 12 7 12 7 mm the bpu was capable of dispatching multiple instructions to the fixed and floating point instructions queues while it was executing a program flow control instruction up to four simultaneously and out of order speculative branches were also supported by using a prediction bit in the branch instructions with the results discarded before being saved if the branch was not taken the alternate instruction would be buffered and discarded if the branch was taken consequently subroutine calls and interrupts are dealt with without incurring branch penalties the condition code register has eight field sets with the first two reserved for fixed and floating point instructions and the seventh for vector instructions the rest of the fields could be used by other instructions the loop register is a counter for decrement and branch on zero loops with no branch penalty a feature similar to those found in some dsps such as the tms320c30 fixed point unit fxu edit the fxu is responsible for decoding and executing all fixed point instructions and floating point load and store instructions for execution the fxu contains the power1 s fixed point register file an arithmetic logic unit alu for general instructions and a dedicated fixed point multiply and divide unit it also contains instruction buffers that receive both fixed and floating point instructions from the icu passing on the floating point instructions to the fpu and a 128 entry two way set associative d tlb for address translation the fxu contains approximately 0 5 million transistors with 0 25 million used for logic and 0 25 used for memory on a die measuring approximately 160 mm² floating point unit fpu edit the power1 s floating point unit executes floating point instructions issue by the icu the fpu is pipelined and can execute single precision 32 bit and double precision 64 bit instructions it is capable of performing multiply add instructions which contributed to the power1 s high floating point performance in most processors a multiply and an add which is common in technical and scientific floating point code cannot be executed in one cycle as in the power1 use of fused multiply add also means that the data is only rounded once improving the precision of the result slightly the floating point register file is also located on the fpu chip it contains 32 64 bit floating point registers six rename registers and two registers that are used by divide instructions data cache unit dcu edit the power1 has a 64 kb data cache implemented through four identical data cache units dcu each containing 16 kb of data cache the cache and the buses that connect the dcu to the other chips are ecc protected the dcus also provide the interface to the memory if two dcus are present rios 9 configuration the memory bus is 64 bits wide and if four dcus are present rios 1 configuration the memory bus is 128 bits wide the memory interface portion of the dcus provide three features that improves the reliability and availability of the memory memory scrubbing ecc and bit steering each dcu contains approximately 1 125 million transistors with 0 175 million used for logic and 0 95 million used for sram on a die measuring approximately 130 mm² 11 3 11 3 mm storage control unit scu edit the power1 is controlled by the scu chip all communications between the icu fxu and dcu chips as well as the memory and i o devices is arbitrated by the scu although the dcus provide the means to perform memory scrubbing it is the scu that controls the process the scu contains approximately 0 23 million transistors all of them for logic on a die measuring approximately 130 mm² i o unit edit the power1 s i o interfaces are implemented by the i o unit which contains an i o channel controller iocc and two serial link adapters slas the iocc implements the micro channel interface and controls both i o and dma transactions between the micro channel adapters and the system memory the two slas each implement a serial fibre optic link which are intended to connect rs 6000 systems together the optical links were not supported at the time of the rs 6000 s release the i o unit contains approximately 0 5 million transistors with 0 3 million used for logic and 0 2 million used for memory on a die measuring approximately 160 mm² see also edit instruction set architectures ibm power instruction set architecture powerpc power isa processors risc single chip rad6000 power2 power3 power4 power5 power6 power7 power8 power9 power10 computer systems rs 6000 scalable powerparallel related technology powerpc 601 rs64 references edit gcc 4 5 release series changes new features and fixes gnu project free software foundation fsf gcc gnu org great microprocessors of the past and present v 13 4 0 montoye r k hokenek e runyon s l january 1990 design of the ibm risc system 6000 floating point execution unit ibm journal of research and development 34 1 59 70 doi 10 1147 rd 341 0059 oehler r r groves r d january 1990 ibm risc system 6000 processor architecture ibm journal of research and development 34 1 23 36 doi 10 1147 rd 341 0023 grohoski g f january 1990 machine organization of the ibm risc system 6000 processor ibm journal of research and development 34 1 37 58 doi 10 1147 rd 341 0037 bakoglu h b grohoski g f montoye r k january 1990 the ibm risc system 6000 processor hardware overview ibm journal of research and development 34 1 12 22 doi 10 1147 rd 341 0012 further reading edit weiss shlomo smith james edward 1994 power and powerpc morgan kaufmann isbn 1558602798 relevant parts chapter 3 how the power architecture is meant to be implemented chapters 4 and 5 describes the power1 retrieved from https en wikipedia org w index php title power1 oldid 1097019669 categories ibm microprocessors superscalar microprocessors 32 bit microprocessors hidden categories articles with short description short description is different from wikidata articles lacking in text citations from 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