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disruptions are created a short circuit develops between the floating gate and the transistor s channel and the floating gate can no longer hold a charge this is the root cause of flash wear out see flash memory memory wear which is specified as the chip s endurance in order to reduce the occurrence of such short circuits floating gate flash is manufactured using a thick tunnel oxide 100å but this slows erase when fowler nordheim tunneling is used and forces the design to use a higher tunneling voltage which puts new burdens on other parts of the chip a charge trapping cell is relatively immune to such difficulties since the charge trapping layer is an insulator 16 a short circuit created by an oxide defect between the charge trapping layer and the channel will drain off only the electrons in immediate contact with the short leaving the other electrons in place to continue to control the threshold voltage of the transistor since short circuits are less of a concern a thinner tunnel oxide layer can be used 50 70å increasing the trapping layer s coupling to the channel and leading to a faster program speed with localized trapped charges and erasing with lower tunneling voltages the lower tunneling voltages in turn place less stress on the tunnel oxide layer leading to fewer lattice disruptions another important benefit of using a charge trapping cell is that the thin charge trapping layer reduces capacitive coupling between neighboring cells to improve performance and scalability 16 getting the charge onto the charge trapping layer edit electrons are moved onto the charge trapping layer similarly to the way that floating gate nor flash is programmed through channel hot electron che injection mechanism also known as hot carrier injection in brief a high voltage is placed between the control gate while a medium high voltage is applied on the source and the drain while a current is induced from the source to the drain those electrons that have gained sufficient energy in traversing through the high field region near the drain will boil off from the channel to be injected into the charge trapping layer where they come to rest removing a charge from the charge trapping layer edit charge trapping flash is erased via hot hole injection see hot carrier injection as opposed to the fowler nordheim tunneling approach used in both nand and nor flash for erasure this process uses a field rather than the current used in fn to move holes toward the charge trapping layer to remove the charge manufacturing charge trapping flash edit charge trapping flash is similar in manufacture to floating gate flash with certain exceptions that serve to simplify manufacturing materials differences from floating gate edit both floating gate flash and charge trapping flash use a stacked gate structure in which a floating gate or charge trapping layer lies immediately above the channel and below a control gate the floating gate or charge trapping layer is insulated from the channel by a tunnel oxide layer and from the control gate by a gate oxide layer materials for all of these layers are the same with the exception of the storage layer which is conductive polysilicon for the floating gate structure and is typically silicon nitride for the charge trap relationship of charge trapping to silicon nanocrystals edit freescale semiconductor manufactures a somewhat similar technology the company calls thin film storage in its microcontroller or mcu line the freescale approach uses silicon nanocrystals as conductive islands in a nonconductive layer of silicon oxide like the more conventional silicon nitride charge trap electrons do not flow from one side of the floating gate to the other extending the cell s wear this nanocrystal approach is being manufactured in volume by freescale and charge trapping storage in general is in development at st microelectronics philips renesas samsung toshiba atmel and spansion 17 process differences from floating gate edit since the nitride charge trapping layer is nonconductive it does not need to be patterned all the charge traps are already insulated from each other this can be used to simplify manufacturing floating gate structures have required more elaborate gate dielectrics for the past few process generations and today commonly use an ono oxide nitride oxide structure which is more complex to manufacture and is unnecessary in a charge trapping flash one advantage of the nitride layer is that it is less sensitive to high temperature fabrication processing than is the polysilicon used in a floating gate this simplifies processing of the layers above the charge trap in a marketing brochure spansion has claimed that the processing cost of a mirrorbit nor flash wafer is lower than that of a conventional floating gate wafer since there are 10 fewer photolithography mask steps and 40 fewer critical steps those requiring the finest resolution and therefore the most expensive photolithographic equipment 18 infineon s marketing materials showed that 15 fewer mask steps were required to make charge trapping nand flash than to manufacture the equivalent floating gate product mirrorbit flash memory edit spansion s mirrorbit flash and saifun s nrom are two flash memories that use a charge trapping mechanism in nitride to store two bits onto the same cell effectively doubling the memory capacity of a chip this is done by placing charges on either side of the charge trap layer the cell is read by using forward and reverse currents through the channel to read either side of the charge trap mirrorbit operation getting 2 bits onto the cell edit figure 2 programming adds electrons to the charge trap through hot electron injection during che programming figure 2 the hot electrons are injected from the channel into the charge trapping layer toward the biased drain end of the channel but not from the floating source end of the channel by allowing the transistor s source and drain to switch from one end of the channel to the other charges can be injected and stored into the charge trapping layer over either end of the channel figure 3 erasing removes electrons from the charge trap through hot hole injection in a similar way one end of the charge trapping cell can be erased by placing the erasing field at one end or the other of the channel allowing the other end to float as shown in figure 3 band to band hot hole erase creates holes that are trapped locally some of which recombine with electrons to remove the charge from that end of the charge trap reading 2 bits from the cell edit the mirrorbit read is performed very simply by reversing the source and drain contacts the junction depletion region extending from the drain side shields the channel from the charge on the side of the charge trapping cell that overlies the drain the net result of this is that the drain side charge has little effect on the current running through the channel while the source side charge determines the threshold of the transistor when source and drain are reversed the opposite side s charge determines the transistor s threshold this way two different charge levels at either end of the charge trapping cell will cause two different currents to flow through the cell depending on the direction of the current flow later developments edit charge trapping nand samsung and others edit samsung electronics in 2006 disclosed 19 its research into the use of charge trapping flash to allow continued scaling of nand technology using cell structures similar to the planar structures in use at that time the technology depends on a sonos silicon oxide nitride oxide silicon or monos metal onos capacitor structure storing the information in charge traps in the nitride layer samsung disclosed two cell structures tanos titanium alumina nitride oxide silicon for 40 nm where researchers believed that the existing 3d cap structure described in detail later in this article could not be manufactured and thnos in which the aluminum oxide would be replaced with an undisclosed high k dielectric material the high k material was expected to yield longer retention times than the aluminum oxide structure in a cap structure the control gate is extended to form a barrier between adjacent floating gates in a conventional floating gate cell over the following five years many device designers found ways to push the cap structure to increasingly tighter process geometries successfully producing nand at the 30 nm node with this approach charge trapping is still viewed as a future technology for nand flash but it is being considered more for vertical structures than for planar cells why nand needs charge trapping technology edit figure 4 process shrinks over time nand flash has been scaling very aggressively figure 4 as processes migrate the width of the interface of the control gate and the floating gate shrinks in proportion to the square of the shrink and the spacing between floating gates shrinks in proportion to the process shrink but the floating gate s thickness remains the same the thinner the floating gate is made the less tolerant the cell becomes to electron loss this means that the coupling between adjacent floating gates becomes larger than the coupling between the control gate and the floating gate leading to data corruption between adjacent bits as processes continue to shrink this becomes increasingly problematic for this reason the control gate in modern nand flash has been reconfigured to cap the floating gate in a cap structure the control gate is extended to form a barrier between adjacent floating gates in a conventional floating gate cell see figure 5 this serves to reduce coupling to the adjacent floating gate while increasing the coupling between the floating gate and the control gate one drawback is that the control gate couples to the channel so measures must be taken to minimize this coupling figure 5 capped cell structure to reduce capacitive coupling between adjacent floating gates it was believed in 2006 that the existing floating gate cap structure could not be manufactured at processes smaller than the 50 nm node due to difficulties in producing the complex three layer ono gate oxide that these devices require samsung even announced 20 in late 2006 that by 2008 it would put such a device into production at the 40 nm process node but over the five years following this announcement many device designers found ways to push the cap structure to increasingly tighter process geometries successfully producing nand down to 20 nm node with this approach the charge trapping approach is still viewed as a future for nand flash for processes smaller than 20 nm and is being considered for both planar as well as vertical 3d structures when this change might occur edit today sandisk asserts that the company expects to continue to use conventional nand structures into a second node in the 10 19 nm range 21 this implies that standard device structures could stay in place until the industry reaches 10 nm however the challenges of producing a reliable floating gate become more severe with each process shrink on the other hand the international technology roadmap for semiconductors itrs process technology roadmap s 2010 process integration devices and structures pids tables 22 show adoption of charge trapping starting at 22 nm in 2012 and becoming mainstream in 2014 with the 20 nm process it is possible that a planar charge trapping cell will be used for future processes no manufacturers have yet disclosed their processes for geometries smaller than 19 nm charge trapping layers for vertical structures edit vertical structures are seen as a logical next step for nand flash once further horizontal scaling becomes inviable since vertical features cannot be etched sideways a charge trapping layer becomes a very interesting way to build a vertical nand flash string toshiba and samsung electronics have disclosed prototypes for vertical charge trapping nand structures toshiba s bics and samsung s 3d nand edit toshiba in 2007 23 and samsung in 2009 24 announced the development of 3d v nand a means of building a standard nand flash bit string vertically rather than horizontally to increase the number of bits in a given area of silicon figure 6 vertical nand structure a rough idea of the cross section of this is shown in figure 6 in this drawing the red portions represent conductive polysilicon the blue is silicon dioxide insulating layers and the yellow is the nitride charge trapping layer the vertical structures only one shown are cylinders that implement a channel that is wrapped in alternating dielectric and charge trapping layers blue and yellow to manufacture such a device layers of conducting polysilicon and silicon dioxide dielectric are deposited first on top of a silicon substrate that contains standard cmos logic elements a trench is then etched and its walls are deposited first with silicon dioxide blue then silicon nitride yellow then another silicon dioxide blue layer forming the gate dielectric the charge trap and the tunnel dielectric in that order finally the hole is filled with conducting polysilicon red which forms the channel the alternating layers of conductive polysilicon function as the control gates in this structure this structure takes advantage of the fact that the charge trap layer does not need to be insulated between each control gate so it need not be etched in the vertical direction charge trapping in embedded memories edit one advantage that charge trapping flash has over other technologies is that it can be relatively easily embedded with a standard logic process a standard logic process can be converted to a logic plus flash process through the addition of three more high voltage masks and three more core ctf masks and none of these six masks is a critical layer i e needs to use the most advanced part of the process all other logic processes can be shared directly 25 bandgap engineered charge trapping memory devices edit in itrs pids 2013 it was clearly mentioned that bandgap engineered charge trapping devices are needed to resolve the retention and erase dilemma sonos using a simple tunnel oxide however is not suitable for nand application once electrons are trapped in deep sin trap levels they are difficult to detrap even under high electric field in order to erase the device quickly holes in the substrate are injected into the sin to neutralize the electron charge since the hole barrier for sio2 is high 4 1 ev hole injection efficiency is poor and sufficient hole current is only achievable by using very thin tunnel oxide 2 nm such thin tunnel oxide however results in poor data retention because direct hole tunneling from the substrate under the weak built in field caused by storage electrons cannot be stopped the rate of direct tunneling is a strong function of the barrier thickness but only weakly depends on the electric field thus the weak built in field by ch...