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neural processing unit wikipedia jump to content main menu main menu move to sidebar hide navigation main page contents current events random article about wikipedia contact us contribute help learn to edit community portal recent changes upload file special pages search search appearance donate create account log in personal tools donate create account log in contents move to sidebar hide top 1 history 2 use toggle use subsection 2 1 consumer devices 2 2 datacenters 2 3 scientific computation 3 programming 4 notes 5 see also 6 references 7 external links toggle the table of contents neural processing unit 22 languages العربية беларуская català čeština deutsch español eesti فارسی suomi français bahasa indonesia italiano 日本語 한국어 polski português română русский shqip українська tiếng việt 中文 edit links article talk english read edit view history tools tools move to sidebar hide actions read edit view history general what links here related changes upload file permanent link page information cite this page get shortened url switch to legacy parser print export download as pdf printable version in other projects wikimedia commons wikidata item appearance move to sidebar hide from wikipedia the free encyclopedia redirected from ai accelerator hardware acceleration unit for artificial intelligence tasks a hailo ai accelerator module attached to a raspberry pi 5 via an m 2 adapter hat 2024 a neural processing unit npu also known as an ai accelerator or deep learning processor is a class of specialized hardware accelerator 1 or computer system 2 3 designed to accelerate artificial intelligence and machine learning applications including artificial neural networks and computer vision npu can be standalone a part of a central processing unit cpu or a part of a graphics processing unit gpu history edit an early use of the term neural processing unit npu to refer to a dedicated neural network accelerator appeared in the 2012 paper neural acceleration for general purpose approximate programs which described an npu architecture for accelerating approximate programs 4 use edit npu s purpose is either to efficiently execute already trained ai models like large language models llms for inference or to train ai models npus can be more efficient in terms of speed or power consumption 5 npu applications include algorithms for robotics internet of things and data intensive or sensor driven tasks 6 they are often manycore or spatial designs and focus on low precision arithmetic novel dataflow architectures or in memory computing capability as of 2024 update a widely used datacenter grade ai integrated circuit chip the nvidia h100 gpu contains tens of billions of metal oxide semiconductor field effect transistors mosfets 7 consumer devices edit ai accelerators are used in apple silicon qualcomm samsung huawei 8 and google tensor smartphone processors 9 when used as part of a gpu for graphics rendering they can significantly reduce resource use by allowing the traditional parts of the gpu to render a scene at a much lower resolution and frame rate e g 540p at 30 frames per second fps and then using a pre trained ai model on the npu to turn that base imagery into smoother and higher resolution output e g 2160p at 240 fps in real time vision processing units are accelerators specialized for machine vision algorithms such as convolutional neural networks cnn and scale invariant feature transform sift they are used in devices that need to keep track of objects visually such as augmented reality ar headsets and drones 10 11 12 it is more recently circa 2017 added to processors from apple 13 and circa 2022 to processors from intel 14 and amd 15 all models of intel meteor lake processors have a built in versatile processor unit vpu for accelerating inference for computer vision and deep learning 16 on consumer devices the npu is intended to be small power efficient but reasonably fast when used to run small models to do this they are designed to support low bitwidth operations using data types such as int4 int8 fp8 and fp16 a common metric is trillions of operations per second tops although tops does not explicitly specify the kind of operations it is typically int8 additions and multiplications 17 datacenters edit the google tensor processing unit tpu v4 package asic in center plus 4 hbm stacks and printed circuit board pcb with 4 liquid cooled packages the board s front panel has 4 top side pcie connectors 2023 accelerators are used in cloud computing servers e g tpus for google cloud platform 18 and trainium and inferentia chips for amazon web services 19 many vendor specific terms exist for devices in this category and it is an emerging technology without a dominant design since the late 2010s gpus designed by companies such as nvidia and amd often include ai specific hardware in the form of dedicated functional units for low precision matrix multiplication operations these gpus are commonly used as ai accelerators both for training and inference 20 scientific computation edit see also scientific computing although npus are tailored for low precision e g fp16 int8 matrix multiplication operations they can be used to emulate higher precision matrix multiplications in scientific computing as modern gpus place much focus on making the npu part fast using emulated fp64 ozaki scheme on npus can potentially outperform native fp64 this has been demonstrated using fp16 emulated fp64 on nvidia titan rtx and using int8 emulated fp64 on nvidia consumer gpus and the a100 gpu consumer gpus especially benefited as they have limited fp64 hardware capacity showing a 6 speedup 21 since cuda toolkit 13 0 update 2 cu blas automatically uses int8 emulated fp64 matrix multiplication of the equivalent precision if it is faster than native this is in addition to the fp16 emulated fp32 feature introduced in version 12 9 22 programming edit an operating system or a higher level library may provide application programming interfaces such as tensorflow with litert next android coreml ios macos or directml windows formats such as onnx are used to represent trained neural networks consumer cpu integrated npus are accessible through vendor specific apis amd ryzen ai intel openvino apple silicon coreml a and qualcomm snpe each have their own apis which can be built upon by a higher level library gpus generally use existing gpgpu pipelines such as cuda and opencl adapted for lower precisions and specialized matrix multiplication operations vulkan is also being used custom built systems such as the google tpu use private interfaces there are a large number of separate underlying acceleration apis and compilers runtimes in use in the ai field causing a great increase in software development effort due to the many combinations involved as of 2025 the open standard organization khronos group is pursuing standardization of ai related interfaces to reduce the amount of work needed khronos is working on three separate fronts expansion of data types and intrinsic operations in opencl and vulkan inclusion of compute graphs in spir v and a nnef skriptnd file format for describing a neural network 23 notes edit mlx builds atop the cpu and gpu parts not the apple neural engine ane part of apple silicon chips the relatively good performance is due to the use of a large fast unified memory design see also edit wetware computer computer composed of organic material ray tracing hardware type of 3d graphics accelerator application specific integrated circuit integrated circuit customized for a specific task references edit page carly july 21 2017 intel unveils movidius compute stick usb ai accelerator v3 archived from the original on august 11 2017 retrieved august 11 2017 inspur unveils gx4 ai accelerator insidehpc june 21 2017 archived from the original on june 21 2017 wiggers kyle november 6 2019 neural magic raises 15 million to boost ai inferencing speed on off the shelf processors venturebeat archived from the original on march 6 2020 esmaeilzadeh hadi sampson adrian ceze luis burger doug 2012 neural acceleration for general purpose approximate programs 2012 45th annual ieee acm international symposium on microarchitecture pp 449 460 doi 10 1109 micro 2012 48 intel core vs ultra how to choose comprehensive guide geekom march 24 2025 retrieved july 5 2026 merritt rick may 18 2016 google designing ai processors ee times retrieved july 5 2026 cite web cs1 maint url status link moss sebastian march 23 2022 nvidia reveals new hopper h100 gpu with 80 billion transistors data center dynamics retrieved july 5 2026 cite web cs1 maint url status link huawei reveals the future of mobile ai at ifa 2017 huawei global september 2 2017 archived from the original on november 10 2021 retrieved january 28 2024 snapdragon 8 gen 3 mobile platform pdf archived from the original pdf on october 25 2023 weckler adrian february 14 2016 dublin tech firm movidius to power google s new virtual reality headset independent ie archived from the original on february 19 2016 retrieved march 15 2016 dji brings two new flagship drones to lineup featuring myriad 2 vpus machine vision technology movidius movidius november 15 2016 archived from the original on november 26 2016 o connor fred may 1 2015 microsoft dives deeper into hololens details holographic processor role revealed pcworld retrieved july 5 2026 cite web cs1 maint url status link the future is here iphone x apple september 12 2017 retrieved july 5 2026 intel s lunar lake processors arriving q3 2024 intel may 20 2024 retrieved july 5 2026 cite web cs1 maint url status link amd xdna architecture amd retrieved july 5 2026 cite web cs1 maint url status link kan michael august 1 2022 intel to bring a vpu processor unit to 14th gen meteor lake chips pcmag retrieved july 5 2026 cite web cs1 maint url status link burns peter april 24 2024 a guide to ai tops and npu performance metrics qualcomm retrieved july 5 2026 cite web cs1 maint url status link jouppi norman p et al june 24 2017 in datacenter performance analysis of a tensor processing unit acm sigarch computer architecture news 45 2 1 12 arxiv 1704 04760 doi 10 1145 3140659 3080246 how silicon innovation became the secret sauce behind aws s success amazon science july 27 2022 retrieved july 5 2026 patel dylan nishball daniel xie myron november 9 2023 nvidia s new china ai chips circumvent us restrictions h20 faster than h100 huawei ascend 910b semianalysis retrieved july 5 2026 ootomo hiroyuki ozaki katsuhisa yokota rio july 2024 dgemm on integer matrix multiplication unit the international journal of high performance computing applications 38 4 297 313 arxiv 2306 11975 doi 10 1177 10943420241239588 brower cole gunnels john lopez graham october 24 2025 unlocking tensor core performance with floating point emulation in cublas nvidia technical blog retrieved july 5 2026 cite web cs1 maint url status link tavenrath markus 2025 current status of ai related standardization in the khronos group pdf global ict standards conference 2025 external links edit nvidia puts the accelerator to the metal with pascal the next platform eyeriss project massachusetts institute of technology v t e hardware acceleration theory universal turing machine parallel computing distributed computing applications gpu gpgpu software directx audio digital signal processing hardware random number generation neural processing unit cryptography tls machine vision custom hardware attack scrypt networking data implementations high level synthesis c to hdl fpga asic cpld system on a chip network on a chip architectures dataflow transport triggered multicore manycore heterogeneous in memory computing systolic array neuromorphic related programmable logic processor design chronology digital electronics virtualization hardware emulation logic synthesis embedded systems retrieved from https en wikipedia org w index php title neural_processing_unit oldid 1376059740 categories application specific integrated circuits neural processing units coprocessors computer optimization gate arrays deep learning hidden categories articles with short description short description is different from wikidata use american english from january 2019 all wikipedia articles written in american english use mdy dates from october 2021 cs1 unfit url articles containing potentially dated statements from 2024 all articles containing potentially dated statements cs1 maint url status this page was last edited on 21 september 2026 at 20 09 utc page was rendered with parsoid text is available under the creative commons attribution sharealike 4 0 license additional terms may apply by using this site you agree to the terms of use and privacy policy wikipedia is a registered trademark of the wikimedia foundation inc a non profit organization privacy policy about wikipedia disclaimers contact wikipedia legal safety contacts code of conduct developers statistics cookie statement mobile view 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