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Text of the page (random words):
eyeriss project eyeriss an energy efficient reconfigurable accelerator for deep convolutional neural networks ieee isscc 2016 yu hsin chen mit tushar krishna mit now with georgia tech joel emer mit nvidia vivienne sze mit email eyeriss at mit dot edu welcome to the eyeriss project website a summary of all related papers can be found here other related websites and resources can be found here follow eems_mit or subscribe to our mailing list for updates on the eyeriss project to find out more about other on going research in the energy efficient multimedia systems eems group at mit please go here we will be giving a two day short course on designing efficient deep learning systems on july 17 18 2023 on mit campus with a virtual option to find out more please visit mit professional education recent news 11 17 2022 updated link to our book on efficient processing of deep neural networks at here 4 17 2020 our book on efficient processing of deep neural networks now available for pre order at here 12 09 2019 video and slides of neurips tutorial on efficient processing of deep neural networks from algorithms to hardware architectures available here 11 11 2019 we will be giving a two day short course on designing efficient deep learning systems at mit in cambridge ma on july 20 21 2020 to find out more please visit mit professional education 5 1 2019 eyeriss is highlighted in mit technology review link 4 21 2019 our paper on eyeriss v2 a flexible accelerator for emerging deep neural networks on mobile devices has been accepted for publication in ieee journal on emerging and selected topics in circuits and systems jetcas paper pdf earlier version arxiv all news abstract eyeriss is an energy efficient deep convolutional neural network cnn accelerator that supports state of the art cnns which have many layers millions of filter weights and varying shapes filter sizes number of filters and channels the test chip features a spatial array of 168 processing elements pe fed by a reconfigurable multicast on chip network that handles many shapes and minimizes data movement by exploiting data reuse data gating and compression are used to reduce energy consumption the chip has been fully integrated with the caffe deep learning framework the video below demonstrates a real time 1000 class image classification task using pre trained alexnet that runs on our eyeriss caffe system the chip can run the convolutions in alexnet at 35 fps with 278 mw power consumption which is 10 times more energy efficient than mobile gpus eyeriss architecture die photo video press coverage mit news the verge ieee spectrum engadget fast company daily mail techaeris techeye pc world downloads paper slides bibtex inproceedings isscc_2016_chen_eyeriss author chen yu hsin and krishna tushar and emer joel and sze vivienne title eyeriss an energy efficient reconfigurable accelerator for deep convolutional neural networks booktitle ieee international solid state circuits conference isscc 2016 digest of technical papers year 2016 pages 262 263 related papers t j yang v sze design considerations for efficient deep neural networks on processing in memory accelerators ieee international electron devices meeting iedm invited paper december 2019 paper pdf slides pdf y h chen t j yang j emer v sze eyeriss v2 a flexible accelerator for emerging deep neural networks on mobile devices ieee journal on emerging and selected topics in circuits and systems jetcas vol 9 no 2 pp 292 308 june 2019 paper pdf earlier version arxiv d wofk f ma t j yang s karaman v sze fastdepth fast monocular depth estimation on embedded systems ieee international conference on robotics and automation icra may 2019 paper pdf poster pdf project website link summary video code github t j yang a howard b chen x zhang a go m sandler v sze h adam netadapt platform aware neural network adaptation for mobile applications european conference on computer vision eccv september 2018 paper arxiv poster pdf project website link code github y h chen t j yang j emer v sze understanding the limitations of existing energy efficient design approaches for deep neural networks sysml conference february 2018 paper pdf talk video selected for oral presentation v sze t j yang y h chen j emer efficient processing of deep neural networks a tutorial and survey proceedings of the ieee vol 105 no 12 pp 2295 2329 december 2017 paper pdf t j yang y h chen j emer v sze a method to estimate the energy consumption of deep neural networks asilomar conference on signals systems and computers invited paper october 2017 paper pdf slides pdf t j yang y h chen v sze designing energy efficient convolutional neural networks using energy aware pruning ieee conference on computer vision and pattern recognition cvpr july 2017 paper arxiv poster pdf dnn energy estimation tool link dnn models link highlighted in mit news y h chen j emer v sze using dataflow to optimize energy efficiency of deep neural network accelerators ieee micro s top picks from the computer architecture conferences may june 2017 pdf a suleiman y h chen j emer v sze towards closing the energy gap between hog and cnn features for embedded vision ieee international symposium of circuits and systems iscas invited paper may 2017 paper pdf slides pdf talk video v sze y h chen j emer a suleiman z zhang hardware for machine learning challenges and opportunities ieee custom integrated circuits conference cicc invited paper may 2017 paper arxiv slides pdf received outstanding invited paper award y h chen t krishna j emer v sze eyeriss an energy efficient reconfigurable accelerator for deep convolutional neural networks ieee journal of solid state circuits jssc isscc special issue vol 52 no 1 pp 127 138 january 2017 pdf y h chen j emer v sze eyeriss a spatial architecture for energy efficient dataflow for convolutional neural networks international symposium on computer architecture isca pp 367 379 june 2016 paper pdf slides pdf selected for ieee micro s top picks special issue on most significant papers in computer architecture based on novelty and long term impact from 2016 y h chen t krishna j emer v sze eyeriss an energy efficient reconfigurable accelerator for deep convolutional neural networks ieee international conference on solid state circuits isscc pp 262 264 february 2016 paper pdf slides pdf poster pdf demo video project website highlighted in eetimes and mit news indicates authors contributed equally to the work related websites and resources dnn tutorial slides link dnn processor benchmarking website link dnn energy estimation website link acknowledgement this work is funded by the darpa yfa grant n66001 14 1 4039 mit center for integrated circuits systems and gifts from intel and nvidia mit eems 2016 accessibility