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the (950), and (345), gate (153), channel (120), mosfet (114), for (108), voltage (107), #transistor (103), with (90), are (90), source (86), drain (82), from (74), text (73), current (70), semiconductor (67), silicon (65), this (63), type (62), that (53), mosfets (51), device (51), which (51), circuits (48), effect (47), metal (47), body (45), high (44), field (43), oxide (43), can (43), devices (42), power (42), mode (42), between (42), isbn (41), when (40), not (38), diode (37), mos (37), used (36), displaystyle (36), threshold (35), layer (35), switch (34), than (34), 978 (33), more (33), dielectric (33), junction (31), depletion (31), nmos (31), region (31), circuit (30), integrated (29), insulator (29), design (29), level (28), other (27), surface (27), transistors (27), inversion (26), low (25), analog (25), also (25), leakage (25), band (24), has (23), off (23), pmos (23), voltages (23), retrieved (22), bulk (22), higher (22), will (22), all (21), cmos (21), logic (21), these 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lectrodes replaced by a semiconductor when a voltage is applied across a mos structure it modifies the distribution of charges in the semiconductor if we consider a p type semiconductor with n a the density of acceptors p the density of holes p n a in neutral bulk a positive voltage v g from gate to body see figure creates a depletion layer by forcing the positively charged holes away from the gate insulator semiconductor interface leaving exposed a carrier free region of immobile negatively charged acceptor ions see doping if v g is high enough a high concentration of negative charge carriers forms in an inversion layer located in a thin layer next to the interface between the semiconductor and the insulator conventionally the gate voltage at which the volume density of electrons in the inversion layer is the same as the volume density of holes in the body is called the threshold voltage when the voltage between transistor gate and source v g exceeds the threshold voltage v th the difference is known as overdrive voltage this structure with p type body is the basis of the n type mosfet which requires the addition of n type source and drain regions mos capacitors and band diagrams this section does not cite any sources please help improve this section by adding citations to reliable sources unsourced material may be challenged and removed january 2019 learn how and when to remove this message the mos capacitor structure is the heart of the mosfet consider a mos capacitor where the silicon base is of p type if a positive voltage is applied at the gate holes which are at the surface of the p type substrate will be repelled by the electric field generated by the voltage applied at first the holes will simply be repelled and what will remain on the surface will be immobile negative atoms of the acceptor type which creates a depletion region on the surface a hole is created by an acceptor atom e g boron which has one less electron than a silicon atom holes are not actually repelled being non entities electrons are attracted by the positive field and fill these holes this creates a depletion region where no charge carriers exist because the electron is now fixed onto the atom and immobile as the voltage at the gate increases there will be a point at which the surface above the depletion region will be converted from p type into n type as electrons from the bulk area will start to get attracted by the larger electric field this is known as inversion the threshold voltage at which this conversion happens is one of the most important parameters in a mosfet in the case of a p type mosfet bulk inversion happens when the intrinsic energy level at the surface becomes smaller than the fermi level at the surface this can be seen on a band diagram the fermi level defines the type of semiconductor in discussion if the fermi level is equal to the intrinsic level the semiconductor is of intrinsic or pure type if the fermi level lies closer to the conduction band valence band then the semiconductor type will be of n type p type when the gate voltage is increased in a positive sense for the given example clarification needed this will shift the intrinsic energy level band so that it will curve downwards towards the valence band if the fermi level lies closer to the valence band for p type there will be a point when the intrinsic level will start to cross the fermi level and when the voltage reaches the threshold voltage the intrinsic level does cross the fermi level and that is what is known as inversion at that point the surface of the semiconductor is inverted from p type into n type if the fermi level lies above the intrinsic level the semiconductor is of n type therefore at inversion when the intrinsic level reaches and crosses the fermi level which lies closer to the valence band the semiconductor type changes at the surface as dictated by the relative positions of the fermi and intrinsic energy levels structure and channel formation see also field effect semiconductor channel formation in nmos mosfet shown as band diagram top panels an applied gate voltage bends bands depleting holes from surface left the charge inducing the bending is balanced by a layer of negative acceptor ion charge right bottom panel a larger applied voltage further depletes holes but conduction band lowers enough in energy to populate a conducting channel c v profile for a bulk mosfet with different oxide thickness the leftmost part of the curve corresponds to accumulation the valley in the middle corresponds to depletion the curve on the right corresponds to inversion a mosfet is based on the modulation of charge concentration by a mos capacitance between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer if dielectrics other than an oxide are employed the device may be referred to as a metal insulator semiconductor fet misfet compared to the mos capacitor the mosfet includes two additional terminals source and drain each connected to individual highly doped regions that are separated by the body region these regions can be either p or n type but they must both be of the same type and of opposite type to the body region the source and drain unlike the body are highly doped as signified by a sign after the type of doping if the mosfet is an n channel or nmos fet then the source and drain are n regions and the body is a p region if the mosfet is a p channel or pmos fet then the source and drain are p regions and the body is a n region the source is so named because it is the source of the charge carriers electrons for n channel holes for p channel that flow through the channel similarly the drain is where the charge carriers leave the channel the occupancy of the energy bands in a semiconductor is set by the position of the fermi level relative to the semiconductor energy band edges see also depletion region with sufficient gate voltage the valence band edge is driven far from the fermi level and holes from the body are driven away from the gate at larger gate bias still near the semiconductor surface the conduction band edge is brought close to the fermi level populating the surface with electrons in an inversion layer or n channel at the interface between the p region and the oxide this conducting channel extends between the source and the drain and current is conducted through it when a voltage is applied between the two electrodes increasing the voltage on the gate leads to a higher electron density in the inversion layer and therefore increases the current flow between the source and drain for gate voltages below the threshold value the channel is lightly populated and only a very small subthreshold leakage current can flow between the source and the drain when a negative gate source voltage positive source gate is applied it creates a p channel at the surface of the n region analogous to the n channel case but with opposite polarities of charges and voltages when a voltage less negative than the threshold value a negative voltage for the p channel is applied between gate and source the channel disappears and only a very small subthreshold current can flow between the source and the drain the device may comprise a silicon on insulator device in which a buried oxide is formed below a thin semiconductor layer if the channel region between the gate dielectric and the buried oxide region is very thin the channel is referred to as an ultrathin channel region with the source and drain regions formed on either side in or above the thin semiconductor layer other semiconductor materials may be employed when the source and drain regions are formed above the channel in whole or in part they are referred to as raised source drain regions comparison of n and p type mosfets 31 parameter nmos fet pmos fet source drain type n type p type channel type mos capacitor n type p type gate type polysilicon n p metal φ m si conduction band φ m si valence band well type p type n type threshold voltage v th positive enhancement negative depletion negative enhancement positive depletion band bending downwards upwards inversion layer carriers electrons holes substrate type p type n type modes of operation source tied to the body to ensure no body bias top left subthreshold top right ohmic mode bottom left active mode at onset of pinch off bottom right active mode well into pinch off channel length modulation evident when the switch is closed the n channel mosfet s gate raises above its threshold voltage so the mosfet then will conduct current to light the led 32 the operation of a mosfet can be separated into three different modes depending on the device s threshold voltage v th displaystyle v_ text th gate to source voltage v gs displaystyle v_ text gs and drain to source voltage v ds displaystyle v_ text ds in the following discussion a simplified algebraic model is used 33 modern mosfet characteristics are more complex than the algebraic model presented here 34 for an enhancement mode n channel mosfet the three operational modes are cutoff subthreshold and weak inversion mode criterion v gs v th displaystyle v_ text gs v_ text th according to the basic threshold model the transistor is turned off and there is no conduction between drain and source a more accurate model considers the effect of thermal energy on the fermi dirac distribution of electron energies which allow some of the more energetic electrons at the source to enter the channel and flow to the drain this results in a subthreshold current that is an exponential function of gate source voltage while the current between drain and source should ideally be zero when the transistor is being used as a turned off switch there is a weak inversion current sometimes called subthreshold leakage in weak inversion where the source is tied to bulk the current varies exponentially with v gs displaystyle v_ text gs as given approximately by 35 36 i d i d0 e v gs v th n v t displaystyle i_ text d approx i_ text d0 e frac v_ text gs v_ text th nv_ text t where i d0 displaystyle i_ text d0 is the current when v gs v th displaystyle v_ text gs v_ text th v t k t q displaystyle v_ text t kt q is the thermal voltage and n displaystyle n is the slope factor given by n 1 c dep c ox displaystyle n 1 frac c_ text dep c_ text ox where c dep displaystyle c_ text dep is the capacitance of the depletion layer and c ox displaystyle c_ text ox is the capacitance of the oxide layer this equation is generally used but is only an adequate approximation for the source tied to the bulk for the source not tied to the bulk the subthreshold equation for drain current in saturation is 37 38 i d i d0 e v g v th n v t e v s v t displaystyle i_ text d approx i_ text d0 e frac v_ text g v_ text th nv_ text t e frac v_ text s v_ text t in a long channel device there is no drain voltage dependence of the current once v ds v t displaystyle v_ text ds gg v_ text t but as channel length is reduced drain induced barrier lowering introduces drain voltage dependence that depends in a complex way upon the device geometry for example the channel doping the junction doping and so on frequently threshold voltage v th for this mode is defined as the gate voltage at which a selected value of current i d0 occurs for example i d0 1 μa which may not be the same v th value used in the equations for the following modes some micropower analog circuits are designed to take advantage of subthreshold conduction 39 40 41 by working in the weak inversion region the mosfets in these circuits deliver the highest possible transconductance to current ratio namely g m i d 1 n v t displaystyle g_ m i_ text d 1 left nv_ text t right almost that of a bipolar transistor 42 the subthreshold i v curve depends exponentially upon threshold voltage introducing a strong dependence on any manufacturing variation that affects threshold voltage for example variations in oxide thickness junction depth or body doping that change the degree of drain induced barrier lowering the resulting sensitivity to fabricational variations complicates optimization for leakage and performance 43 44 mosfet drain current vs drain to source voltage for several values of v gs v th displaystyle v_ text gs v_ text th the boundary between linear ohmic and saturation active modes is indicated by the upward curving parabola cross section of a mosfet operating in the linear ohmic region strong inversion region present even near drain cross section of a mosfet operating in the saturation active region channel exhibits channel pinching near drain triode mode or linear region also known as the ohmic mode criteria v gs v th displaystyle v_ text gs v_ text th and v ds v gs v th displaystyle v_ text ds v_ text gs v_ text th the transistor is turned on and a channel has been created which allows current between the drain and the source the mosfet operates like a resistor controlled by the gate voltage relative to both the source and drain voltages the current from drain to source is modeled as i d μ n c ox w l v gs v t h v ds v ds 2 2 displaystyle i_ text d mu _ n c_ text ox frac w l left left v_ text gs v_ rm th right v_ text ds frac v_ text ds 2 2 right where μ n displaystyle mu _ n is the charge carrier effective mobility w displaystyle w is the gate width l displaystyle l is the gate length and c ox displaystyle c_ text ox is the gate oxide capacitance per unit area the transition from the exponential subthreshold region to the triode region is not as sharp as the equations suggest 45 46 verification needed saturation or active mode criteria v gs v th displaystyle v_ text gs v_ text th and v ds v gs v th displaystyle v_ text ds geq v_ text gs v_ text th the switch is turned on and a channel has been created which allows current between the drain and source since the drain voltage is higher than the source voltage the electrons spread out and conduction is not through a narrow channel but through a broader two or three dimensional current distribution extending away from the interface and deeper in the substrate the onset of this region is also known as pinch off to indicate the lack of channel region near the drain although the channel does not extend the full length of the device the electric field between the drain and the channel is very high and conduction continues the drain current is now weakly dependent upon drain voltage and controlled primarily by the gate source voltage and modeled approximately as i d μ n c ox 2 w l v gs v th 2 1 λ v ds displaystyle i_ text d frac mu _ n c_ text ox 2 frac w l left v_ text gs v_ text th right 2 left 1 lambda v_ text ds right the additional factor involving λ the channel length modulation parameter models current dependence on drain voltage due to the early effect or channel length modulation according to this equation a key design parameter the mosfet transconductance is g m i d v gs 2 i d v gs v th 2 i...
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