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on cite this page get shortened url switch to legacy parser print export download as pdf printable version in other projects wikimedia commons wikidata item appearance move to sidebar hide from wikipedia the free encyclopedia computer bus standard physically based on eurocard sizes this article includes a list of general references but lacks sufficient corresponding inline citations please help improve this article by introducing more precise citations april 2009 learn how and when to remove this message vme64 crate with from left an adc module a scaler module and a processor module vmebus versamodule eurocard bus 1 bus is a computer bus standard physically based on eurocard sizes history edit in 1979 during development of the motorola 68000 cpu one of their engineers jack kister decided to set about creating a standardized bus system for 68000 based systems 2 the motorola team brainstormed for days to select the name versabus versabus cards were large 370 by 230 mm 14 1 2 by 9 1 4 in and used edge connectors 1 only a few products adopted it including the ibm system 9000 instrument controller and the automatix robot and machine vision systems versabus memory card kister was later joined by john black who refined the specifications and created the versamodule product concept a young engineer working for black julie keahey designed the first versamodule card the versabus adaptor module used to run existing cards on the new versabus sven rau and max loesel of motorola europe added a mechanical specification to the system basing it on the eurocard standard that was then late in the standardization process the result was first known as versabus e but was later renamed to vmebus for versamodule eurocard bus although some refer to it as versa module europe or versa module european 1 at this point a number of other companies involved in the 68000 s ecosystem agreed to use the standard including signetics philips thomson and mostek soon it was officially standardized by the iec as the iec 821 vmebus and by ansi and ieee as ansi ieee 1014 1987 the original standard described a bus with up to 16 bit width designed to fit within the existing eurocard din connectors and which has a maximum transfer bandwidth of 40 mb s 3 however there have been several updates to the system to allow wider bus widths the current vme64 supports up to 64 bit bus width in 6u sized cards and 32 bit in 3u cards doubling the bus width also doubles the maximum transfer bandwidth of vme64 to 80 mb s 4 other associated standards have added hot swapping plug and play and doubling bandwidth in vme64x 5 smaller ip cards that plug into a single vmebus card and various interconnect standards for linking vme systems together in the late 1990s synchronous protocols proved to be favourable the research project was called vme320 the vita standards organization called for a new standard for unmodified vme32 64 backplanes 6 the new 2esst protocol was approved in ansi vita 1 5 in 1999 over the years many extensions have been added to the vme interface providing sideband channels of communication in parallel to vme itself some examples are ip module raceway interlink scsa gigabit ethernet on vme64x backplanes pci express rapidio starfabric and infiniband vmebus was also used to develop closely related standards vxibus and vpx the vmebus had a strong influence on many later computer buses such as stebus vme early years edit the architectural concepts of the vmebus are based on versabus developed in the late 1970s by motorola this was later renamed vme short for versamodule eurocard by lyman lym hevle then a vp with the motorola microsystems operation 1 7 lyman was later in 1982 the founder of the vmebus marketing group itself subsequently renamed to vmebus international trade association in 1984 1985 8 9 since shortened to vita in 2005 8 10 john black of motorola craig mackenna of mostek and cecil kaplinsky of signetics developed the first draft of the vmebus specification in october 1981 at the system 81 trade show in munich west germany motorola mostek signetics philips and thomson csf announced their joint support of the vmebus they also placed revision a of the specification in the public domain in 1985 aitech developed under contract for us army tacom the first conduction cooled 6u vmebus board although electrically providing a compliant vmebus protocol interface mechanically this board was not interchangeable for use in air cooled lab vmebus development chassis in late 1987 a technical committee was formed under vita under the direction of ieee to create the first military conduction cooled 6u 160 mm fully electrically and mechanically compatible vmebus board co chaired by dale young dy4 systems and doug patterson plessey microsystems then radstone technology ansi ieee 1101 2 1992 was later ratified and released in 1992 and remains in place as the conduction cooled international standard for all 6u vmebus products in 1989 john peters of performance technologies inc developed the initial concept of vme64 multiplexing address and data lines a64 d64 on the vmebus the concept was demonstrated the same year and placed in the vita technical committee in 1990 as a performance enhancement to the vmebus specification in 1993 new activities began on the base vme architecture involving the implementation of high speed serial and parallel sub buses for use as i o interconnections and data mover subsystems these architectures can be used as message switches routers and small multiprocessor parallel architectures vita s application for recognition as an accredited standards developer organization of ansi was granted in june 1993 numerous other documents including mezzanine p2 and serial bus standards have been placed with vita as the public domain administrator of these technologies evolution of vme topology year bus cycle maximum speed mb s vmebus32 parallel bus rev a 1981 blt 40 vmebus ieee 1014 1987 blt 40 vme64 1994 mblt 80 vme64x 1997 2evme 160 vme320 1997 2esst 320 description edit in many ways the vmebus is equivalent or analogous to the pins of the 68000 run out onto a backplane however one of the key features of the 68000 is a flat 32 bit memory model free of memory segmentation and other anti features the result is that while vme is very 68000 like the 68000 is generic enough to make this not an issue in most cases like the 68000 vme uses separate 32 bit data and address buses the 68000 address bus is actually 24 bit and the data bus 16 bit although it is 32 32 internally but the designers were already looking towards a full 32 bit implementation in order to allow both bus widths vme uses two different eurocard connectors p1 and p2 p1 contains three rows of 32 pins each implementing the first 24 address bits 16 data bits and all of the control signals p2 contains one more row which includes the remaining 8 address bits and 16 data bits a block transfer protocol allows several bus transfers to occur with a single address cycle in block transfer mode the first transfer includes an address cycle and subsequent transfers require only data cycles the slave is responsible for ensuring that these transfers use successive addresses bus masters can release the bus in two ways with release when done rwd the master releases the bus when it completes a transfer and must re arbitrate for the bus before every subsequent transfer with release on request ror the master retains the bus by continuing to assert bbsy between transfers ror allows the master to retain control over the bus until a bus clear bclr is asserted by another master that wishes to arbitrate for the bus thus a master that generates bursts of traffic can optimize its performance by arbitrating for the bus on only the first transfer of each burst this decrease in transfer latency comes at the cost of somewhat higher transfer latency for other masters address modifiers are used to divide the vme bus address space into several distinct sub spaces the address modifier is a 6 bit wide set of signals on the backplane address modifiers specify the number of significant address bits the privilege mode to allow processors to distinguish between bus accesses by user level or system level software and whether or not the transfer is a block transfer below is an incomplete table of address modifiers hex code function explanation 3f standard supervisory block transfer block transfer a24 privileged 3e standard supervisory program access a24 instruction access privileged 3d standard supervisor data access a24 data access privileged 3b standard non privileged block transfer a24 block transfer for normal programs 3a standard non privileged program access a24 instruction access non privileged 39 standard non privileged data access a24 data access non privileged 2d short supervisory access a16 privileged access 29 short non privileged access a16 non privileged access 0f extended supervisory block transfer a32 privileged block transfer 0e extended supervisory program access a32 privileged instruction access 0d extended supervisory data access a32 privileged data access 0b extended non privileged block transfer a32 non privileged block transfer 0a extended non privileged program access a32 non privileged instruction access 09 extended non privileged data access a32 non privileged data access note a n as in a16 a24 a32 refers to the width of the address on the vme bus all transfers are dma and every card is a master or slave in most bus standards there is a considerable amount of complexity added in order to support various transfer types and master slave selection for instance with the isa bus both of these features had to be added alongside the existing channels model whereby all communications was handled by the host cpu this makes vme considerably simpler at a conceptual level while being more powerful though it requires more complex controllers on each card development tools edit when developing and or troubleshooting the vme bus examination of hardware signals can be very important logic analyzers and bus analyzers are tools that collect analyze decode store signals so people can view the high speed waveforms at their leisure vita offers a comprehensive faq to assist with the front end design and development of vme systems computers using a vmebus edit computers using vmebus include hp 743 744 pa risc single board computer 11 sun 2 through sun 4 hp 9000 industrial workstations atari tt030 and atari mega ste motorola mvme symbolics advanced numerical research and analysis group s pace etas es1000 rapid prototyping system several motorola 88000 based data general aviion computers early silicon graphics mips based systems including professional iris personal iris power series and onyx systems convergent technologies mightyframe pinout edit this section does not cite any sources please help improve this section by adding citations to reliable sources unsourced material may be challenged and removed may 2020 learn how and when to remove this message seen looking into backplane socket 12 13 p1 pin a b c 1 d00 bbsy d08 2 d01 bclr d09 3 d02 acfail d10 4 d03 bg0in d11 5 d04 bg0out d12 6 d05 bg1in d13 7 d06 bg1out d14 8 d07 bg2in d15 9 gnd bg2out gnd 10 sysclk bg3in sysfail 11 gnd bg3out berr 12 ds1 br0 sysreset 13 ds0 br1 lword 14 write br2 am5 15 gnd br3 a23 16 dtack am0 a22 17 gnd am1 a21 18 as am2 a20 19 gnd am3 a19 20 iack gnd a18 21 iackin serclk a17 22 iackout serdat a16 23 am4 gnd a15 24 a07 irq7 a14 25 a06 irq6 a13 26 a05 irq5 a12 27 a04 irq4 a11 28 a03 irq3 a10 29 a02 irq2 a09 30 a01 irq1 a08 31 12v 5vstdby 12v 32 5v 5v 5v p2 pin a b c 1 user defined 5v user defined 2 user defined gnd user defined 3 user defined reserved user defined 4 user defined a24 user defined 5 user defined a25 user defined 6 user defined a26 user defined 7 user defined a27 user defined 8 user defined a28 user defined 9 user defined a29 user defined 10 user defined a30 user defined 11 user defined a31 user defined 12 user defined gnd user defined 13 user defined 5v user defined 14 user defined d16 user defined 15 user defined d17 user defined 16 user defined d18 user defined 17 user defined d19 user defined 18 user defined d20 user defined 19 user defined d21 user defined 20 user defined d22 user defined 21 user defined d23 user defined 22 user defined gnd user defined 23 user defined d24 user defined 24 user defined d25 user defined 25 user defined d26 user defined 26 user defined d27 user defined 27 user defined d28 user defined 28 user defined d29 user defined 29 user defined d30 user defined 30 user defined d31 user defined 31 user defined gnd user defined 32 user defined 5v user defined p2 rows a and c can be used by a secondary bus for example the stebus see also edit data acquisition vpx vxs futurebus compactpci camac fpdp list of device bandwidths references edit 1 2 3 4 vmebus technology faq introduction to vmebus vita com retrieved 19 february 2026 black john arthur 1992 the system engineer s handbook a guide to building vmebus and vxibus systems morgan kaufmann p 563 isbn 978 0 12 102820 6 a team of engineers at motorola microsystems led by jack kister designed a 68000 development system called the exormacs the backplane of the exormacs was called versabus while coordinating the efforts of his team jack wrote a 41 page bus description of versabus which was published in november of 1979 the first exormacs was shipped in january 1980 vmebus technology faq original vmebus ieee 1014 1987 vita com retrieved 19 february 2026 vmebus technology faq vme64 vita com retrieved 19 february 2026 vmebus technology faq the vme64 extensions vme64x vita com retrieved 19 february 2026 vmebus technology faq vme320 vita com retrieved 19 february 2026 vita history vita com retrieved 19 february 2026 1 2 about vita vita com retrieved 19 february 2026 vita history 1985 vita com retrieved 19 february 2026 vita history 2005 vita com retrieved 19 february 2026 hp vme products alimar technology corp alimartech com retrieved 1 august 2013 from table 7 1 j1 p1 pin assignments ansi vita 1 1994 r2002 from table 7 2 j2 p2 pin assignments ansi vita 1 1994 r2002 external links edit vita website vmebus technology faq next generation vme vme bus pinout and signals v t e technical and de facto standards for wired computer buses general system bus front side bus back side bus daisy chain control bus address bus bus contention bus mastering network on a chip plug and play double data rate quad data rate list of bus bandwidths standards ss 50 bus s 100 bus multibus unibus vaxbi mbus std bus smbus q bus europe card bus isa stebus zorro ii zorro iii camac fastbus lpc hp precision bus eisa vme vxi vxs vpx nubus turbochannel mca sbus vlb hp gsc bus infiniband ethernet upa pci pci extended pci x pxi pci express pcie agp compute express link cxl direct media interface dmi rapidio intel quickpath interconnect nvlink hypertransport infinity fabric intel ultra path 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