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Text of the page (random words):
index the cache and does not use any tags false cache hits may occur which is solved by tagging with the virtual address the speed of this recurrence the load latency is crucial to cpu performance and so most modern level 1 caches are virtually indexed which at least allows the mmu s tlb lookup to proceed in parallel with fetching the data from the cache ram but virtual indexing is not the best choice for all cache levels the cost of dealing with virtual aliases grows with cache size and as a result most level 2 and larger caches are physically indexed caches have historically used both virtual and physical addresses for the cache tags although virtual tagging is now uncommon if the tlb lookup can finish before the cache ram lookup then the physical address is available in time for tag compare and there is no need for virtual tagging large caches then tend to be physically tagged and only small very low latency caches are virtually tagged in recent general purpose cpus virtual tagging has been superseded by virtual hints as described below homonym and synonym problems edit a cache that relies on virtual indexing and tagging becomes inconsistent after the same virtual address is mapped into different physical addresses homonym which can be solved by using physical address for tagging or by storing the address space identifier in the cache line however the latter approach does not help against the synonym problem in which several cache lines end up storing data for the same physical address writing to such locations may update only one location in the cache leaving the others with inconsistent data this issue may be solved by using non overlapping memory layouts for different address spaces or otherwise the cache or a part of it must be flushed when the mapping changes 34 virtual tags and hints edit the great advantage of virtual tags is that for associative caches they allow the tag match to proceed before the virtual to physical translation is done however coherence probes and evictions present a physical address for action the hardware must have some means of converting the physical addresses into a cache index generally by storing physical tags as well as virtual tags for comparison a physically tagged cache does not need to keep virtual tags which is simpler when a virtual to physical mapping is deleted from the tlb cache entries with those virtual addresses will have to be flushed somehow alternatively if cache entries are allowed on pages not mapped by the tlb then those entries will have to be flushed when the access rights on those pages are changed in the page table it is also possible for the operating system to ensure that no virtual aliases are simultaneously resident in the cache the operating system makes this guarantee by enforcing page coloring which is described below some early risc processors sparc rs 6000 took this approach it has not been used recently as the hardware cost of detecting and evicting virtual aliases has fallen and the software complexity and performance penalty of perfect page coloring has risen it can be useful to distinguish the two functions of tags in an associative cache they are used to determine which way of the entry set to select and they are used to determine if the cache hit or missed the second function must always be correct but it is permissible for the first function to guess and get the wrong answer occasionally some processors e g early sparcs have caches with both virtual and physical tags the virtual tags are used for way selection and the physical tags are used for determining hit or miss this kind of cache enjoys the latency advantage of a virtually tagged cache and the simple software interface of a physically tagged cache it bears the added cost of duplicated tags however also during miss processing the alternate ways of the cache line indexed have to be probed for virtual aliases and any matches evicted the extra area and some latency can be mitigated by keeping virtual hints with each cache entry instead of virtual tags these hints are a subset or hash of the virtual tag and are used for selecting the way of the cache from which to get data and a physical tag like a virtually tagged cache there may be a virtual hint match but physical tag mismatch in which case the cache entry with the matching hint must be evicted so that cache accesses after the cache fill at this address will have just one hint match since virtual hints have fewer bits than virtual tags distinguishing them from one another a virtually hinted cache suffers more conflict misses than a virtually tagged cache perhaps the ultimate reduction of virtual hints can be found in the pentium 4 willamette and northwood cores in these processors the virtual hint is effectively two bits and the cache is four way set associative effectively the hardware maintains a simple permutation from virtual address to cache index so that no content addressable memory cam is necessary to select the right one of the four ways fetched page coloring edit main article cache coloring large physically indexed caches usually secondary caches run into a problem the operating system rather than the application controls which pages collide with one another in the cache differences in page allocation from one program run to the next lead to differences in the cache collision patterns which can lead to very large differences in program performance these differences can make it very difficult to get a consistent and repeatable timing for a benchmark run to understand the problem consider a cpu with a 1 mib physically indexed direct mapped level 2 cache and 4 kib virtual memory pages sequential physical pages map to sequential locations in the cache until after 256 pages the pattern wraps around we can label each physical page with a color of 0 255 to denote where in the cache it can go locations within physical pages with different colors cannot conflict in the cache programmers attempting to make maximum use of the cache may arrange their programs access patterns so that only 1 mib of data need be cached at any given time thus avoiding capacity misses but they should also ensure that the access patterns do not have conflict misses one way to think about this problem is to divide up the virtual pages the program uses and assign them virtual colors in the same way as physical colors were assigned to physical pages before programmers can then arrange the access patterns of their code so that no two pages with the same virtual color are in use at the same time there is a wide literature on such optimizations e g loop nest optimization largely coming from the high performance computing hpc community the snag is that while all the pages in use at any given moment may have different virtual colors some may have the same physical colors in fact if the operating system assigns physical pages to virtual pages randomly and uniformly it is extremely likely that some pages will have the same physical color and then locations from those pages will collide in the cache this is the birthday paradox the solution is to have the operating system attempt to assign different physical color pages to different virtual colors a technique called page coloring although the actual mapping from virtual to physical color is irrelevant to system performance odd mappings are difficult to keep track of and have little benefit so most approaches to page coloring simply try to keep physical and virtual page colors the same if the operating system can guarantee that each physical page maps to only one virtual color then there are no virtual aliases and the processor can use virtually indexed caches with no need for extra virtual alias probes during miss handling alternatively the os can flush a page from the cache whenever it changes from one virtual color to another as mentioned above this approach was used for some early sparc and rs 6000 designs the software page coloring technique has been used to effectively partition the shared last level cache llc in multicore processors 35 this operating system based llc management in multicore processors has been adopted by intel 36 cache hierarchy in a modern processor edit memory hierarchy of an amd bulldozer server modern processors have multiple interacting on chip caches the operation of a particular cache can be completely specified by the cache size the cache block size the number of blocks in a set the cache set replacement policy and the cache write policy write through or write back 25 while all of the cache blocks in a particular cache are the same size and have the same associativity typically the higher level caches called level 1 cache have a smaller number of blocks smaller block size and fewer blocks in a set but have very short access times lower level caches i e level 2 and below have progressively larger numbers of blocks larger block size more blocks in a set and relatively longer access times but are still much faster than main memory 8 cache entry replacement policy is determined by a cache algorithm selected to be implemented by the processor designers in some cases multiple algorithms are provided for different kinds of work loads specialized caches edit pipelined cpus access memory from multiple points in the pipeline instruction fetch virtual to physical address translation and data fetch see classic risc pipeline the natural design is to use different physical caches for each of these points so that no one physical resource has to be scheduled to service two points in the pipeline thus the pipeline naturally ends up with at least three separate caches instruction tlb and data each specialized to its particular role victim cache edit main article victim cache a victim cache is a cache used to hold blocks evicted from a cpu cache upon replacement the victim cache lies between the main cache and its refill path and holds only those blocks of data that were evicted from the main cache the victim cache is usually fully associative and is intended to reduce the number of conflict misses many commonly used programs do not require an associative mapping for all the accesses in fact only a small fraction of the memory accesses of the program require high associativity the victim cache exploits this property by providing high associativity to only these accesses it was introduced by norman jouppi from dec in 1990 37 intel s crystalwell 38 variant of its haswell processors introduced an on package 128 mib edram level 4 cache which serves as a victim cache to the processors level 3 cache 39 in the skylake microarchitecture the level 4 cache no longer works as a victim cache 40 trace cache edit main article trace cache one of the more extreme examples of cache specialization is the trace cache also known as execution trace cache found in the intel pentium 4 microprocessors a trace cache is a mechanism for increasing the instruction fetch bandwidth and decreasing power consumption in the case of the pentium 4 by storing traces of instructions that have already been fetched and decoded 41 a trace cache stores instructions either after they have been decoded or as they are retired generally instructions are added to trace caches in groups representing either individual basic blocks or dynamic instruction traces the pentium 4 s trace cache stores micro operations resulting from decoding x86 instructions providing also the functionality of a micro operation cache having this the next time an instruction is needed it does not have to be decoded into micro ops again 42 63 68 write coalescing cache wcc edit write coalescing cache 43 is a special cache that is part of l2 cache in amd s bulldozer microarchitecture stores from both l1d caches in the module go through the wcc where they are buffered and coalesced the wcc s task is reducing number of writes to the l2 cache micro operation μop or uop cache edit a micro operation cache μop cache uop cache or uc 44 is a specialized cache that stores micro operations of decoded instructions as received directly from the instruction decoders or from the instruction cache when an instruction needs to be decoded the μop cache is checked for its decoded form which is re used if cached if it is not available the instruction is decoded and then cached one of the early works describing μop cache as an alternative frontend for the intel p6 processor family is the 2001 paper micro operation cache a power aware frontend for variable instruction length isa 45 later intel included μop caches in its sandy bridge processors and in successive microarchitectures like ivy bridge and haswell 42 121 123 46 amd implemented a μop cache in their zen microarchitecture 47 fetching complete pre decoded instructions eliminates the need to repeatedly decode variable length complex instructions into simpler fixed length micro operations and simplifies the process of predicting fetching rotating and aligning fetched instructions a μop cache effectively offloads the fetch and decode hardware thus decreasing power consumption and improving the frontend supply of decoded micro operations the μop cache also increases performance by more consistently delivering decoded micro operations to the backend and eliminating various bottlenecks in the cpu s fetch and decode logic 45 46 a μop cache has many similarities with a trace cache although a μop cache is much simpler thus providing better power efficiency this makes it better suited for implementations on battery powered devices the main disadvantage of the trace cache leading to its power inefficiency is the hardware complexity required for its heuristic deciding on caching and reusing dynamically created instruction traces 48 branch target instruction cache edit a branch target cache or branch target instruction cache the name used on arm microprocessors 49 is a specialized cache which holds the first few instructions at the destination of a taken branch this is used by low powered processors which do not need a normal instruction cache because the memory system is capable of delivering instructions fast enough to satisfy the cpu without one however this only applies to consecutive instructions in sequence it still takes several cycles of latency to restart instruction fetch at a new address causing a few cycles of pipeline bubble after a control transfer a branch target cache provides instructions for those few cycles avoiding a delay after most taken branches this allows full speed operation with a much smaller cache than a traditional full time instruction cache smart cache edit smart cache is a level 2 or level 3 caching method for multiple execution cores developed by intel smart cache shares the actual cache memory between the cores of a multi core processor in comparison to a dedicated per core cache the overall cache miss rate decreases when cores do not require equal parts of the cache space consequently a single core can use the full level ...
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