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the (950), and (345), gate (153), #channel (120), mosfet (114), for (108), voltage (107), transistor (103), with (90), are (90), source (86), drain (82), from (74), text (73), current (70), semiconductor (67), silicon (65), this (63), type (62), that (53), mosfets (51), device (51), which (51), circuits (48), effect (47), metal (47), body (45), high (44), field (43), oxide (43), can (43), devices (42), power (42), mode (42), between (42), isbn (41), when (40), not (38), diode (37), mos (37), used (36), displaystyle (36), threshold (35), layer (35), switch (34), than (34), 978 (33), more (33), dielectric (33), junction (31), depletion (31), nmos (31), region (31), circuit (30), integrated (29), insulator (29), design (29), level (28), other (27), surface (27), transistors (27), inversion (26), low (25), analog (25), also (25), leakage (25), band (24), has (23), off (23), pmos (23), voltages (23), retrieved (22), bulk (22), higher (22), will (22), all (21), cmos (21), logic (21), these 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potential to turn the switch on the pmos switch passes all voltages higher than v gate v threshold_pmos note enhancement mode pmos fets have a negative threshold voltage but passes higher voltages better than lower ones dual type cmos main article transmission gate electronic switch the cmos analog switch passes the signal through both a pmos qp and an nmos qn when st is high the switch provides a low resistance between ua and ub either of which could be considered the input or output this complementary or cmos type of switch uses one pmos and one nmos fet connected in parallel to counteract the limitations of the single type switch 61 when used in digital logic it is called a transmission gate the fets have their drains and sources connected in parallel the body of the pmos is connected to the high potential vpos in diagram and the body of the nmos is connected to the low potential vneg to turn the switch on the gate of the pmos is driven to the low potential and the gate of the nmos is driven to the high potential for voltages between vpos v threshold_nmos and vneg v threshold_pmos both fets conduct the signal though with the nmos passing lower voltages better while the pmos passes higher voltages better for voltages less than vneg v threshold_pmos the nmos conducts alone for voltages greater than vpos v threshold_nmos the pmos conducts alone the voltage limits for this switch are the gate source gate drain and source drain voltage limits for both fets also the pmos is typically two to three times wider than the nmos so the switch will be balanced for speed in the two directions tri state circuitry sometimes incorporates a cmos mosfet switch on its output to provide for a low ohmic full range output when on and a high ohmic mid level signal when off construction gate material the primary criterion for the gate material is that it is a good conductor highly doped polycrystalline silicon is an acceptable but certainly not ideal conductor and also suffers from some more technical deficiencies in its role as the standard gate material nevertheless there are several reasons favoring use of polysilicon the threshold voltage and consequently the drain to source on current is modified by the work function difference between the gate material and channel material because polysilicon is a semiconductor its work function can be modulated by adjusting the type and level of doping furthermore because polysilicon has the same bandgap as the underlying silicon channel it is quite straightforward to tune the work function to achieve low threshold voltages for both nmos and pmos devices by contrast the work functions of metals are not easily modulated so tuning the work function to obtain low threshold voltages lvt becomes a significant challenge additionally obtaining low threshold devices on both pmos and nmos devices sometimes requires the use of different metals for each device type the silicon sio 2 interface has been well studied and is known to have relatively few defects by contrast many metal insulator interfaces contain significant levels of defects which can lead to fermi level pinning charging or other phenomena that ultimately degrade device performance in the mosfet ic fabrication process it is preferable to deposit the gate material prior to certain high temperature steps in order to make better performing transistors such high temperature steps would melt some metals limiting the types of metal that can be used in a metal gate based process while polysilicon gates have been the de facto standard for the last twenty years they do have some disadvantages which have led to their likely future replacement by metal gates these disadvantages include polysilicon is not a great conductor approximately 1000 times more resistive than metals which reduces the signal propagation speed through the material the resistivity can be lowered by increasing the level of doping but even highly doped polysilicon is not as conductive as most metals to improve conductivity further sometimes a high temperature metal such as tungsten titanium cobalt and more recently nickel is alloyed with the top layers of the polysilicon such a blended material is called silicide the silicide polysilicon combination has better electrical properties than polysilicon alone and still does not melt in subsequent processing also the threshold voltage is not significantly higher than with polysilicon alone because the silicide material is not near the channel the process in which silicide is formed on both the gate electrode and the source and drain regions is sometimes called salicide self aligned silicide when the transistors are extremely scaled down it is necessary to make the gate dielectric layer very thin around 1 nm in state of the art technologies a phenomenon observed here is the so called poly depletion where a depletion layer is formed in the gate polysilicon layer next to the gate dielectric when the transistor is in the inversion to avoid this problem a metal gate is desired a variety of metal gates such as tantalum tungsten tantalum nitride and titanium nitride are used usually in conjunction with high κ dielectrics an alternative is to use fully silicided polysilicon gates a process known as fusi present high performance cpus use metal gate technology together with high κ dielectrics a combination known as high κ metal gate hkmg the disadvantages of metal gates are overcome by a few techniques 62 the threshold voltage is tuned by including a thin work function metal layer between the high κ dielectric and the main metal this layer is thin enough that the total work function of the gate is influenced by both the main metal and thin metal work functions either due to alloying during annealing or simply due to the incomplete screening by the thin metal the threshold voltage thus can be tuned by the thickness of the thin metal layer high κ dielectrics are now well studied and their defects are understood hkmg processes exist that do not require the metals to experience high temperature anneals other processes select metals that can survive the annealing step insulator as devices are made smaller insulating layers are made thinner often through steps of thermal oxidation or localised oxidation of silicon locos for nano scaled devices at some point tunneling of carriers through the insulator from the channel to the gate electrode takes place to reduce the resulting leakage current the insulator can be made thinner by choosing a material with a higher dielectric constant to see how thickness and dielectric constant are related note that gauss s law connects field to charge as q κ ϵ 0 e displaystyle q kappa epsilon _ 0 e with q charge density κ dielectric constant ε 0 permittivity of empty space and e electric field from this law it appears the same charge can be maintained in the channel at a lower field provided κ is increased the voltage on the gate is given by v g v ch e t ins v ch q t ins κ ϵ 0 displaystyle v_ text g v_ text ch e t_ text ins v_ text ch frac qt_ text ins kappa epsilon _ 0 with v g gate voltage v ch voltage at channel side of insulator and t ins insulator thickness this equation shows the gate voltage will not increase when the insulator thickness increases provided κ increases to keep t ins κ constant see the article on high κ dielectrics for more detail and the section in this article on gate oxide leakage the insulator in a mosfet is a dielectric which can in any event be silicon oxide formed by locos but many other dielectric materials are employed the generic term for the dielectric is gate dielectric since the dielectric lies directly below the gate electrode and above the channel of the mosfet junction design the source to body and drain to body junctions are the object of much attention because of three major factors their design affects the current voltage i v characteristics of the device lowering output resistance and also the speed of the device through the loading effect of the junction capacitances and finally the component of stand by power dissipation due to junction leakage mosfet showing shallow junction extensions raised source and drain and halo implant raised source and drain are separated from gate by oxide spacers the drain induced barrier lowering of the threshold voltage and channel length modulation effects upon i v curves are reduced by using shallow junction extensions in addition halo doping can be used that is the addition of very thin heavily doped regions of the same doping type as the body tight against the junction walls to limit the extent of depletion regions 63 the capacitive effects are limited by using raised source and drain geometries that make most of the contact area border thick dielectric instead of silicon 64 these various features of junction design are shown with artistic license in the figure scaling this section is written like a personal reflection personal essay or argumentative essay that states a wikipedia editor s personal feelings or presents an original argument about a topic please help improve it by rewriting it in an encyclopedic style september 2016 learn how and when to remove this message further information dennard scaling trend of intel cpu transistor gate length mosfet version of gain boosted current mirror m 1 and m 2 are in active mode while m 3 and m 4 are in ohmic mode and act like resistors the operational amplifier provides feedback that maintains a high output resistance over the past decades the mosfet as used for digital logic has continually been scaled down in size typical mosfet channel lengths were once several micrometres but modern integrated circuits are incorporating mosfets with channel lengths of tens of nanometers robert dennard s work on scaling theory was pivotal in recognising that this ongoing reduction was possible intel began production of a process featuring a 32 nm feature size with the channel being even shorter in late 2009 the semiconductor industry maintains a roadmap the itrs 65 which sets the pace for mosfet development historically the difficulties with decreasing the size of the mosfet have been associated with the semiconductor device fabrication process the need to use very low voltages and with poorer electrical performance necessitating circuit redesign and innovation small mosfets exhibit higher leakage currents and lower output resistance smaller mosfets are desirable for several reasons the main reason to make transistors smaller is to pack more and more devices in a given chip area this results in a chip with the same functionality in a smaller area or chips with more functionality in the same area since fabrication costs for a semiconductor wafer are relatively fixed the cost per integrated circuits is mainly related to the number of chips that can be produced per wafer hence smaller ics allow more chips per wafer reducing the price per chip in fact over the past 30 years the number of transistors per chip has been doubled every 2 3 years once a new technology node is introduced for example the number of mosfets in a microprocessor fabricated in a 45 nm technology can well be twice as many as in a 65 nm chip this doubling of transistor density was first observed by gordon moore in 1965 and is commonly referred to as moore s law 66 it is also expected that smaller transistors switch faster for example one approach to size reduction is a scaling of the mosfet that requires all device dimensions to reduce proportionally the main device dimensions are the channel length channel width and oxide thickness when they are scaled down by equal factors the transistor channel resistance does not change while gate capacitance is cut by that factor hence the rc delay of the transistor scales with a similar factor while this has been traditionally the case for the older technologies for the state of the art mosfets reduction of the transistor dimensions does not necessarily translate to higher chip speed because the delay due to interconnections is more significant producing mosfets with channel lengths much smaller than a micrometre is a challenge and the difficulties of semiconductor device fabrication are always a limiting factor in advancing integrated circuit technology though processes such as ald have improved fabrication for small components the small size of the mosfet less than a few tens of nanometers has created operational problems higher subthreshold conduction as mosfet geometries shrink the voltage that can be applied to the gate must be reduced to maintain reliability to maintain performance the threshold voltage of the mosfet has to be reduced as well as threshold voltage is reduced the transistor cannot be switched from complete turn off to complete turn on with the limited voltage swing available the circuit design is a compromise between strong current in the on case and low current in the off case and the application determines whether to favor one over the other subthreshold leakage including subthreshold conduction gate oxide leakage and reverse biased junction leakage which was ignored in the past now can consume upwards of half of the total power consumption of modern high performance vlsi chips 67 68 increased gate oxide leakage the gate oxide which serves as insulator between the gate and channel should be made as thin as possible to increase the channel conductivity and performance when the transistor is on and to reduce subthreshold leakage when the transistor is off however with current gate oxides with a thickness of around 1 2 nm which in silicon is 5 atoms thick the quantum mechanical phenomenon of electron tunneling occurs between the gate and channel leading to increased power consumption silicon dioxide has traditionally been used as the gate insulator silicon dioxide however has a modest dielectric constant increasing the dielectric constant of the gate dielectric allows a thicker layer while maintaining a high capacitance capacitance is proportional to dielectric constant and inversely proportional to dielectric thickness all else equal a higher dielectric thickness reduces the quantum tunneling current through the dielectric between the gate and the channel insulators that have a larger dielectric constant than silicon dioxide referred to as high κ dielectrics such as group ivb metal silicates e g hafnium and zirconium silicates and oxides are being used to reduce the gate leakage from the 45 nanometer technology node onwards on the other hand the barrier height of the new gate insulator is an important consideration the difference in conduction band energy between the semiconductor and the dielectric and the corresponding difference in valence band energy also affects leakage current level for the traditional gate oxide silicon dioxide the former barrier is approximately 8 ev for many alternative dielectrics the value is significantly lower tending to increase the tunneling current somewhat ne...
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