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Text of the page (random words):
lected transistors such that the memory cannot be altered writeable variants of rom such as eeprom and nor flash share properties of both rom and ram enabling data to persist without power and to be updated without requiring special equipment ecc memory which can be either sram or dram includes special circuitry to detect and or correct random faults memory errors in the stored data using parity bits or error correction codes in general the term ram refers solely to solid state memory devices either dram or sram and more specifically the main memory in most computers in optical storage the term dvd ram is somewhat of a misnomer since unlike cd rw or dvd rw it does not need to be erased before reuse nevertheless a dvd ram behaves much like a hard disc drive if somewhat slower memory cell main article memory cell computing the memory cell is the fundamental building block of computer memory the memory cell is an electronic circuit that stores one bit of binary information and it must be set to store a logic 1 high voltage level and reset to store a logic 0 low voltage level its value is maintained stored until it is changed by the set reset process the value in the memory cell can be accessed by reading it in sram the memory cell is a type of flip flop circuit usually implemented using fets this means that sram requires very low power when not being accessed but it is expensive and has low storage density a second type dram is based around a capacitor charging and discharging this capacitor can store a 1 or a 0 in the cell however the charge in this capacitor slowly leaks away and must be refreshed periodically because of this refresh process dram uses more power but it can achieve greater storage densities and lower unit costs compared to sram sram cell 6 transistors dram cell 1 transistor and one capacitor addressing to be useful memory cells must be readable and writeable within the ram device multiplexing and demultiplexing circuitry is used to select memory cells typically a ram device has a set of address lines a0 an and for each combination of bits that may be applied to these lines a set of memory cells are activated due to this addressing ram devices virtually always have a memory capacity that is a power of two usually several memory cells share the same address for example a 4 bit wide ram chip has 4 memory cells for each address often the width of the memory and that of the microprocessor are different for a 32 bit microprocessor eight 4 bit ram chips would be needed often more addresses are needed than can be provided by a device in that case external multiplexors to the device are used to activate the correct device that is being accessed memory hierarchy main article memory hierarchy one can read and over write data in ram many computer systems have a memory hierarchy consisting of processor registers on die sram caches external caches dram paging systems and virtual memory or swap space on a hard drive this entire pool of memory may be referred to as ram by many developers even though the various subsystems can have very different access times violating the original concept behind the random access term in ram even within a hierarchy level such as dram the specific row column bank rank channel or interleave organization of the components make the access time variable although not to the extent that access time to rotating storage media or a tape is variable the overall goal of using a memory hierarchy is to obtain the highest possible average access performance while minimizing the total cost of the entire memory system generally the memory hierarchy follows the access time with the fast cpu registers at the top and the slow hard drive at the bottom in many modern personal computers the ram comes in an easily upgraded form of modules called memory modules or dram modules about the size of a few sticks of chewing gum these can quickly be replaced should they become damaged or when changing needs demand more storage capacity as suggested above smaller amounts of ram mostly sram are also integrated in the cpu and other ics on the motherboard as well as in hard drives cd roms and several other parts of the computer system other uses of ram a so dimm stick of laptop ram roughly half the size of desktop ram in addition to serving as temporary storage and working space for the operating system and applications ram is used in numerous other ways virtual memory main article virtual memory most modern operating systems employ a method of extending ram capacity known as virtual memory a portion of the computer s hard drive is set aside for a paging file or a scratch partition and the combination of physical ram and the paging file form the system s total memory for example if a computer has 2 gb 1024 3 b of ram and a 1 gb page file the operating system has 3 gb total memory available to it when the system runs low on physical memory it can swap portions of ram to the paging file to make room for new data as well as to read previously swapped information back into ram excessive use of this mechanism results in thrashing and generally hampers overall system performance mainly because hard drives are far slower than ram ram disk main article ram drive software can partition a portion of a computer s ram allowing it to act as a much faster hard drive that is called a ram disk a ram disk loses the stored data when the computer is shut down unless memory is arranged to have a standby battery source or changes to the ram disk are written out to a nonvolatile disk the ram disk is reloaded from the physical disk upon ram disk initialization shadow ram sometimes the contents of a relatively slow rom chip are copied to read write memory to allow for shorter access times the rom chip is then disabled while the initialized memory locations are switched in on the same block of addresses often write protected this process sometimes called shadowing is fairly common in both computers and embedded systems as a common example the bios in typical personal computers often has an option called use shadow bios or similar when enabled functions that rely on data from the bios s rom instead use dram locations most can also toggle shadowing of video card rom or other rom sections depending on the system this may not result in increased performance and may cause incompatibilities for example some hardware may be inaccessible to the operating system if shadow ram is used on some systems the benefit may be hypothetical because the bios is not used after booting in favor of direct hardware access free memory is reduced by the size of the shadowed roms 27 recent developments several new types of non volatile ram which preserve data while powered down are under development the technologies used include carbon nanotubes and approaches utilizing tunnel magnetoresistance amongst the 1st generation mram a 128 kbit 128 2 10 bytes chip was manufactured with 0 18 µm technology in the summer of 2003 citation needed in june 2004 infineon technologies unveiled a 16 mb 16 2 20 bytes prototype again based on 0 18 µm technology there are two 2nd generation techniques currently in development thermal assisted switching tas 28 which is being developed by crocus technology and spin transfer torque stt on which crocus hynix ibm and several other companies are working 29 nantero built a functioning carbon nanotube memory prototype 10 gb 10 2 30 bytes array in 2004 whether some of these technologies can eventually take significant market share from either dram sram or flash memory technology however remains to be seen since 2006 solid state drives based on flash memory with capacities exceeding 256 gigabytes and performance far exceeding traditional disks have become available this development has started to blur the definition between traditional random access memory and disks dramatically reducing the difference in performance some kinds of random access memory such as ecoram are specifically designed for server farms where low power consumption is more important than speed 30 memory wall the memory wall is the growing disparity of speed between cpu and memory outside the cpu chip an important reason for this disparity is the limited communication bandwidth beyond chip boundaries which is also referred to as bandwidth wall from 1986 to 2000 cpu speed improved at an annual rate of 55 while memory speed only improved at 10 given these trends it was expected that memory latency would become an overwhelming bottleneck in computer performance 31 cpu speed improvements slowed significantly partly due to major physical barriers and partly because current cpu designs have already hit the memory wall in some sense intel summarized these causes in a 2005 document 32 first of all as chip geometries shrink and clock frequencies rise the transistor leakage current increases leading to excess power consumption and heat secondly the advantages of higher clock speeds are in part negated by memory latency since memory access times have not been able to keep pace with increasing clock frequencies third for certain applications traditional serial architectures are becoming less efficient as processors get faster due to the so called von neumann bottleneck further undercutting any gains that frequency increases might otherwise buy in addition partly due to limitations in the means of producing inductance within solid state devices resistance capacitance rc delays in signal transmission are growing as feature sizes shrink imposing an additional bottleneck that frequency increases don t address the rc delays in signal transmission were also noted in clock rate versus ipc the end of the road for conventional microarchitectures 33 which projected a maximum of 12 5 average annual cpu performance improvement between 2000 and 2014 a different concept is the processor memory performance gap which can be addressed by 3d integrated circuits that reduce the distance between the logic and memory aspects that are further apart in a 2d chip 34 memory subsystem design requires a focus on the gap which is widening over time 35 the main method of bridging the gap is the use of caches small amounts of high speed memory that houses recent operations and instructions nearby the processor speeding up the execution of those operations or instructions in cases where they are called upon frequently multiple levels of caching have been developed to deal with the widening gap and the performance of high speed modern computers relies on evolving caching techniques 36 there can be up to a 53 difference between the growth in speed of processor and the lagging speed of main memory access 37 solid state hard drives have continued to increase in speed from 400 mbit s via sata3 in 2012 up to 3 gb s via nvme pcie in 2018 closing the gap between ram and hard disk speeds although ram continues to be an order of magnitude faster with single lane ddr4 3200 capable of 25 gb s and modern gddr even faster fast cheap non volatile solid state drives have replaced some functions formerly performed by ram such as holding certain data for immediate availability in server farms 1 terabyte of ssd storage can be had for 200 while 1 tb of ram would cost thousands of dollars 38 39 timeline see also flash memory timeline read only memory timeline and transistor count memory sram static random access memory sram date of introduction chip name capacity bits access time sram type manufacturer s process mosfet ref march 1963 1 bit bipolar cell fairchild 9 1965 8 bit bipolar ibm sp95 16 bit bipolar ibm 40 64 bit mosfet fairchild pmos 41 1966 tmc3162 16 bit bipolar ttl transitron 8 mosfet nec 42 1968 64 bit mosfet fairchild pmos 42 144 bit mosfet nec nmos 512 bit mosfet ibm nmos 41 1969 128 bit bipolar ibm 9 1101 256 bit 850 ns mosfet intel 12 000 nm pmos 43 44 45 46 1972 2102 1 kbit mosfet intel nmos 43 1974 5101 1 kbit 800 ns mosfet intel cmos 43 47 2102a 1 kbit 350 ns mosfet intel nmos depletion 43 48 1975 2114 4 kbit 450 ns mosfet intel nmos 43 47 1976 2115 1 kbit 70 ns mosfet intel nmos hmos 43 44 2147 4 kbit 55 ns mosfet intel nmos hmos 43 49 1977 4 kbit mosfet toshiba cmos 44 1978 hm6147 4 kbit 55 ns mosfet hitachi 3 000 nm cmos twin well 49 tms4016 16 kbit mosfet texas instruments nmos 44 1980 16 kbit mosfet hitachi toshiba cmos 50 64 kbit mosfet matsushita 1981 16 kbit mosfet texas instruments 2 500 nm nmos 50 october 1981 4 kbit 18 ns mosfet matsushita toshiba 2 000 nm cmos 51 1982 64 kbit mosfet intel 1 500 nm nmos hmos 50 february 1983 64 kbit 50 ns mosfet mitsubishi cmos 52 1984 256 kbit mosfet toshiba 1 200 nm cmos 50 45 1987 1 mbit mosfet sony hitachi mitsubishi toshiba cmos 50 december 1987 256 kbit 10 ns bimos texas instruments 800 nm bicmos 53 1990 4 mbit 15 23 ns mosfet nec toshiba hitachi mitsubishi cmos 50 1992 16 mbit 12 15 ns mosfet fujitsu nec 400 nm december 1994 512 kbit 2 5 ns mosfet ibm cmos soi 54 1995 4 mbit 6 ns cache syncburst hitachi 100 nm cmos 55 256 mbit mosfet hyundai cmos 56 dram dynamic random access memory dram date of introduction chip name capacity bits dram type manufacturer s process mosfet area ref 1965 1 bit dram cell toshiba 16 17 1967 1 bit dram cell ibm mos 19 42 1968 256 bit dram ic fairchild pmos 8 1969 1 bit dram cell intel pmos 42 1970 1102 1 kbit dram ic intel honeywell pmos 42 1103 1 kbit dram intel 8 000 nm pmos 10 mm² 57 58 20 1971 μpd403 1 kbit dram nec nmos 59 2 kbit dram general instrument pmos 13 mm² 60 1972 2107 4 kbit dram intel nmos 43 61 1973 8 kbit dram ibm pmos 19 mm² 60 1975 2116 16 kbit dram intel nmos 62 8 1977 64 kbit dram ntt nmos 35 mm² 60 1979 mk4816 16 kbit psram mostek nmos 63 64 kbit dram siemens vmos 25 mm² 60 1980 256 kbit dram nec ntt 1 000 1 500 nm nmos 34 42 mm² 60 1981 288 kbit dram ibm mos 25 mm² 64 1983 64 kbit dram intel 1 500 nm cmos 20 mm² 60 256 kbit dram ntt cmos 31 mm² january 5 1984 8 mbit dram hitachi mos 65 66 february 1984 1 mbit dram hitachi nec 1 000 nm nmos 74 76 mm² 60 67 ntt 800 nm cmos 53 mm² 60 67 1984 tms4161 64 kbit dpram vram texas instruments nmos 68 69 january 1985 μpd41264 256 kbit dpram vram nec nmos 70 71 june 1986 1 mbit psram toshiba cmos 72 1986 4 mbit dram nec 800 nm nmos 99 mm² 60 texas instruments toshiba 1 000 nm cmos 100 137 mm² 1987 16 mbit dram ntt 700 nm cmos 148 mm² 60 october 1988 512 kbit hsdram ibm 1 000 nm cmos 78 mm² 73 1991 64 mbit dram matsushita mitsubishi fujitsu toshiba 400 nm cmos 50 1993 256 mbit dram hitachi nec 250 nm cmos 1995 4 mbit dpram vram hitachi cmos 55 january 9 1995 1 gbit dram nec 250 nm cmos 74 55 hitachi 160 nm cmos 1996 4 mbit fram samsung nmos 75 1997 4 gbit qlc nec 150 nm cmos 50 1998 4 gbit dram hyundai cmos 56 june 2001 tc51w3216xb 32 mbit psram toshiba cmos 76 february 2001 4 gbit dram samsung 100 nm cmos 50 77 sdram part of this section is transcluded from synchronous dynamic random access memory edit history synchronous dynamic random access memory sdram date of introduction ch...
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