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system security innovation with real world impact by tianyin xu hubertus franke a team of researchers from university of illinois at urbana champaign carnegie mellon university ibm and redhat affiliated with the ibm illinois c3sr center have upstreamed their work on operating system os security to the linux kernel as reported by phoronix one of the largest open source news sites the feature named constant action bitmaps is yielding a very nice speedup for system call security a cornerstone for protecting shared os kernels continue reading last updated on wed apr 28 2021 1 min read acm student research competition first place winner the c3sr student mert hidayetoglu has won the firt place winner award from the very competitive acm student research competition out of 12 acm student research competition posters that were accepted at sc20 three finalists were asked to give an additional presentation of their work the c3sr student mert hidayetoglu s presentation finally took the trophy and won the first place winner award mert will move on to the grand finale next year and compete with the winners of 22 acm sponsored conferences continue reading last updated on wed apr 28 2021 1 min read sc20 best paper award the c3sr student mert hidayetoglu and c3sr faculty prof wen mei hwu together with their collaborators have won the best paper award at sc20 for their paper titled petascale xct 3d image reconstruction with hierarchical communications on multi gpu nodes this year sc20 accepted 95 papers for its proceedings after an extensive double blind review of 378 submissions nine papers were nominated for the best paper award and the paper led by mert hidayetoglu won the award continue reading publications more publications leveraging dynamic partial reconfiguration with scalable ilp based task scheduling a dhar m yu w zuo x wang n s kim d chen 2020 33nd international conference on vlsi design and 2020 19th international conference on embedded systems vlsid 2020 nais neural architecture and implementation search and its applications in autonomous driving the rapidly growing demands for powerful ai algorithms in many application domains have motivated massive investment in both high quality deep neural network dnn models and high efficiency implementations in this position paper we argue that a simultaneous dnn implementation co design methodology named neural architecture and implementation search nais deserves more research attention to boost the development productivity and efficiency of both dnn models and implementation optimization we propose a stylized design methodology that can drastically cut down the search cost while preserving the quality of the end solution as an illustration we discuss this dnn implementation methodology in the context of both fpgas and gpus we take autonomous driving as a key use case as it is one of the most demanding areas for high quality ai algorithms and accelerators we discuss how such a co design methodology can impact the autonomous driving industry significantly we identify several research opportunities in this exciting domain c hao y chen x liu a sarwari d sew a dhar b wu d fu j xiong w hwu j gu d chen international conference on computer aided design 2019 learning motion in feature space locally consistent deformable convolution networks for fine grained action detection fine grained action detection is an important task with numerous applications in robotics and human computer interaction existing methods typically utilize a two stage approach including extraction of local spatio temporal features followed by temporal modeling to capture long term dependencies while most recent papers have focused on the latter long temporal modeling here we focus on producing features capable of modeling fine grained motion more efficiently we propose a novel locally consistent deformable convolution which utilizes the change in receptive fields and enforces a local coherency constraint to capture motion information effectively our model jointly learns spatio temporal features instead of using independent spatial and temporal streams the temporal component is learned from the feature space instead of pixel space e g optical flow the produced features can be flexibly used in conjunction with other long temporal modeling networks e g st cnn dilatedtcn and ed tcn overall our proposed approach robustly outperforms the original long temporal models on two fine grained action datasets 50 salads and gtea achieving f1 scores of 80 22 and 75 39 respectively khoi nguyen c mac dhiraj joshi raymond a yeh jinjun xiong rogerio s feris minh n do international conference on computer vision 2019 pdf spgnet semantic prediction guidance for scene parsing multi scale context module and single stage encoder decoder structure are commonly employed for semantic segmentation the multi scale context module refers to the operations to aggregate feature responses from a large spatial extent while the single stage encoder decoder structure encodes the high level semantic information in the encoder path and recovers the boundary information in the decoder path in contrast multi stage encoder decoder networks have been widely used in human pose estimation and show superior performance than their single stage counterpart however few efforts have been attempted to bring this effective design to semantic segmentation in this work we propose a semantic prediction guidance spg module which learns to re weight the local features through the guidance from pixel wise semantic prediction we find that by carefully re weighting features across stages a two stage encoder decoder network coupled with our proposed spg module can significantly outperform its one stage counterpart with similar parameters and computations finally we report experimental results on the semantic segmentation benchmark cityscapes in which our spgnet attains 81 1 on the test set using only fine annotations b cheng l c chen y wei y zhu z huang j xiong t huang w m hwu h shi international conference on computer vision 2019 pdf deepstore in storage acceleration for intelligent queries recent advancements in deep learning techniques facilitate intelligentquery support in diverse applications such as content based image retrieval and audio texturing unlike conventional key based queries these intelligent queries lack efficient indexing and require complex compute operations for feature matching to achieve highperformance intelligent querying against massive datasets modern computing systems employ gpus in conjunction with solid state drives ssds for fast data access and parallel data processing however our characterization with various intelligent query workloads developed with deep neural networks dnns shows that the storage i o bandwidth is still the major bottleneck that contributes 56 90 of the query execution time to this end we present deepstore an in storage accelerator architecture for intelligent queries it consists of 1 energy efficient in storage accelerators designed specifically for supporting dnnbased intelligent queries under the resource constraints in modern ssd controllers 2 a similarity based in storage query cache to exploit the temporal locality of user queries for further performance improvement and 3 a lightweight in storage runtime system working as the query engine which provides a simple software abstraction to support different types of intelligent queries deepstore exploits ssd parallelisms with design space exploration for achieving the maximal energy efficiency for in storage accelerators we validate deepstore design with an ssd simulator and evaluate it with a variety of vision text and audio based intelligent queries compared with the state of the art gpu ssd approach deepstore improves the query performance by up to 17 7 and energy efficiency by up to 78 6 v s mailthdoy z qureshi w liang z feng s gonzalo y li h franke j xiong j huang w hwu proceedings of the 52 annual ieee acm international symposium on microarchitecture micro 19 2019 pdf accelerating sparse deep neural networks on fpgas deep neural networks dnns have been widely adopted in many domains including computer vision natural language processing and medical care recent research reveals that sparsity in dnn parameters can be exploited to reduce inference computational complexity and improve network quality however sparsity also introduces irregularity and extra complexity in data processing which make the accelerator design challenging this work presents the design and implementation of a highly flexible sparse dnn inference accelerator on fpga our proposed inference engine can be easily configured to be used in both mobile computing and high performance computing scenarios evaluation shows our proposed inference engine effectively accelerates sparse dnns and outperforms cpu solution by up to 4 7x in terms of energy efficiency s huang c pearson r nagi j xiong w hwu d chen ieee high performance extreme computing conference 2019 pdf large scale mixed bandwidth deep neural network acoustic modeling for automatic speech recognition in automatic speech recognition asr wideband wb and narrowband nb speech signals with different sampling rates typically use separate acoustic models therefore mixed bandwidth mb acoustic modeling has important practical values for asr system deployment in this paper we extensively investigate large scale mb deep neural network acoustic modeling for asr using 1 150 hours of wb data and 2 300 hours of nb data we study various mb strategies including downsampling upsampling and bandwidth extension for mb acoustic modeling and evaluate their performance on 8 diverse wb and nb test sets from various application domains to deal with the large amounts of training data distributed training is carried out on multiple gpus using synchronous data parallelism khoi nguyen c mac xiaodong cui wei zhang michael picheny international speech communication association 2019 pdf analysis and optimization of i o cache coherency strategies for soc fpga device unlike traditional pcie based fpga accelerators heterogeneous soc fpga devices provide tighter integrations between software running on cpus and hardware accelerators modern heterogeneous soc fpga platforms support multiple i o cache coherence options between cpus and fpgas but these options can have inadvertent effects on the achieved bandwidths depending on applications and data access patterns to provide the most efficient communications between cpus and accelerators understanding the data transaction behaviors and selecting the right i o cache coherence method is essential in this paper we use xilinx zynq ultrascale as the soc platform to show how certain i o cache coherence method can perform better or worse in different situations ultimately affecting the overall accelerator performances as well based on our analysis we further explore possible software and hardware modifications to improve the i o performances with different i o cache coherence options with our proposed modifications the overall performance of soc design can be averagely improved by 20 s min s huang m el hadedy j xiong d chen w hwu international conference on field programmable logic and applications 2019 2019 update on triangle counting on gpu this work presents an update to the triangle counting portion of the subgraph isomorphism static graph challenge this work is motivated by a desire to understand the impact of cuda unified memory on the triangle counting problem first cuda unified memory is used to overlap reading large graph data from disk with graph data structures in gpu memory second we use cuda unified memory hintsto solve multi gpu performance scaling challenges present in our last submission finally we improve the single gpu kernel performance from our past submission by introducing a work stealing dynamic algorithm gpu kernel with persistent threads which makes performance adaptive for large graphs withoutrequiring a graph analysis phase carl pearson mohammad almasri omer anjum vikram s mailthody zaid qureshi rakesh nagi jinjun xiong wen mei hwu 2019 ieee high performance extreme computing conference 2019 update on k truss decomposition on gpu in this paper we present an update to our previous submission on k truss decomposition from graph challenge 2018 for single gpu k truss implementation we propose multiple algorithmic optimizations that significantly improve performance by up to 35 2x 6 9x on average compared to our previous gpu implementation in addition we present a scalable multi gpu implementation in which each gpu handles a different k value compared to our prior multi gpu implementation the proposed approach is faster by up to 151 3x 78 8x on average in case when the edges with only maximal k truss are sought incrementing the k value in each iteration is inefficient particularly for graphs with large maximum k truss thus we propose binary search for the k value to find the maximal k truss the binary search approach on a single gpu is up to 101 5 24 3x on average faster than our 2018 k truss submission lastly we show that the proposed binary search finds the maximum k truss for twitter graph dataset having 2 8 billion bidirectional edges in just 16 minutes on a single v100 gpu mohammad almasri omer anjum carl pearson vikram s mailthody zaid qureshi rakesh nagi jinjun xiong wen mei hwu 2019 ieee high performance extreme computing conference 2019 invited talks keynote speeach cognitive computing on heterogeneous hardware systems for the ai revolution sun oct 20 2019 ieee international workshop on signal processing systems deming chen keynote speeach cognitive computing on heterogeneous hardware systems for the ai revolution tue jul 16 2019 computing conference 2019 deming chen video invited distinguished speaker design compilation and acceleration for deep neural networks in iot applications wed apr 17 2019 ieee symposium on low power and high speed chips and systems cool chips 22 deming chen pdf cloud tools and libraries for exploriting heterogeneous cognitive computing systems wed sep 27 2017 openpower workshop at hpcxxl j xiong w hwu a dakkak c li and c pearson architecture and software for emerging low power systems mon jul 24 2017 keynote for the international symposium on low power electronics and design islped w hwu j xiong n kim d chen i hajj a dakkak l chang s garcia and c pearson slides crowdsensing crowdsourcing and creativity thu jun 1 2017 plenary talk for the international association for world englishes iawe lav r varshney slides cognitive computing on heterogeneous hardware systems for the ai revolution sat jul 8 2017 shanghaitech workshop on emerging devices circuits and systems deming chen slides innovative applications and technology pivots a perfect storm in computing sat feb 11 2017 uci department of computer science distinguished lecture series w w hwu j xiong a dakkak and c pearson slides awards more ...