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Text of the page (random words):
3806 function timing chips the 3805 dip18 includes the adder subtractor as well as a 25 bit register the accumulator this accumulator was maskable as well allowing different parts of it to be operated on with a 6 bit mask this allowed a great amount of flexibility in programming the 3806 chip the largest of the chipset a dip24 contains the timing and control logic two 25 bit status registers branch logic the instruction address register and various other logic functions to support this core is a pair of register chips the 3808 and 3809 registers these are basic shift registers and each contain three 4 bit bcd parallel 25 digit serial register memories instructions are stored in up to 25 256 12 bit serial roms the 3810 the address bus is 8 bits and the instruction word is 12 bits so with 25 chips you get 6400 instruction words of available instructions or constants 95 instructions were provided cybernetic mathiputer vintagecomputer net the pps 25 also supports the 3811 for handling output as well as the 3807 3803 input devices which support up to a 32 key keyboard 3807 or larger 3803 both these chips came in 40dip packages larger then the cpu itself this design was a bit complicated and took several chips so it did not see wide adoption fairchild de emphasized it by 1974 as they were working then on the f8 processor the pps 25 did however find its uses and inspired other designs as well hp considered using the pps 25 in its calculator designs before deciding to make their own cpu s in house saturn nut etc the design and programming of which bare a strong resemblance to the pps 25 one of the more known uses of the pps 25 was in the cybernetic mathiputer an early learning toy for children but its use was not limited to such trivial devices it was also used where precise math work was needed a walsh spectrum analyser design chose it above the what would normally be considered much more powerful intel 8080 largely due to its math capabilities 3805 alu 4 bit its turns out making a cpu function more like an advanced calculator allowed it to do advanced math fairly well it was also chosen for calculating sinc cosc values for an engineering system piper cheyenne ii another field where precise math is needed is in navigation and the pps 25 found a home here as well king radio corp now honeywell designed a radio navigation computer for airplanes in the 1970s based on the pps 25 around 500 of these were made and were found in such planes as the piper pa 31t cheyenne cessna 441 conquest ii and beech king air high end twin turbo props of the era interestingly king had difficulties sourcing replacements for these so a common upgrade to these nav computers was replacing the pps 25 with a custom asic and a motorola 6802 cpu posted in cpu of the day march 19th 2024 by admin national semi pace ins8900 test boards in 1974 national semiconductor introduced what is arguably the first 16 bit microprocessor it had a 8 bit mode as well which was more efficient but could run 16 bits as well this chip was made on a pmos process and ran at 1 3mhz in some ways it was ahead of its time there wasn t a ton of demand for a 16 bit processor at the time and interfacing to its pmos architecture was tricky the pace used 12v 8v as well as 5v it also required a high power 2 phase clock the clock drove the internal logic national was to use signetics and rockwell as second sources but neither ended up making chips this was a 2 way agreement as national was to second source the 2650 for signetics and the pps 4 pps 8 for rockwell the pace had a 10 level 16 bit stack and 4 16 bit general purpose registers it supported 46 instructions national semi ipc 16a 500d pace 1977 the pace found a very few design wins mostly used in custom applications where its speed and 16 bit were useful it was designed into a custom control system for a concrete batch plant and later in 1980 used by cern in switzerland to control a touch terminal used for particle accelerator experiments specifically controlling the modal terminal for the super proton synchrotron in this application its speed and its 16 bit capabilities were useful for the math functions needed cern eventually replaced it with the much easier to work with motorola mc68000 which had euro sources available a similar use was found by the australians dept of defense to control a graphics terminal also used for physics experiments cern nodal touch terminal powered by pace in 1977 national converted the design to nmos which simplified its interfacing and increased the speed to 2mhz this was the ins8900 which required 8vdc 12v and 5v but most importantly a normal single phase clock the ins8900 also fixed a few bugs some sources claim the ins8900 also added a nop instruction but this existed officially in the pace as well opcode 5c00 in addition sflg pflg 0000 can be used as a nop on either processor the ins8900 was used in a very early multi processor system designed by brato british rail automatic train operation this system was an early investigation of automating train track control and used three ins8900 cpus to provide enough speed and redundancy to run the 3 programs deemed needed automatic driver tachometer and safety supervisor each processor each program so all 3 processors eventually run all 3 programs and then the results are compared the ins8900 was chosen over the tms9900 because it utilized the bus much less the tms9900 user registers use external ram whereas the ins8900 has 4 general purpose internal registers resulting in less chances of bus interference between the 3 processors the ins8900d was also used in some sun not the sun microsystems motor testers used in automotive repair sops in the early 1980 s ins8900d 1979 early production large black die cap ins 8900d 1985 late production small gold die cap these processors are a bit obscure and as far as i can tell were not used in a ton of products they do come up from time to time though and the cpu shack now has a test board design available for them the board was a challenge to build due to the pace and the ins8900 having such different voltages and clocks requiring separate power supply panels to run each these are now available for pre order we re not thinking to generally stock these quite yet price is 159 and includes free shipping worldwide pre order now and i should be able to ship in around 6 weeks if there is enough interest i will of course try to keep 1 2 in stock for that time you find a nice white gold ipc 16 pace cpu posted in boards and systems cpu of the day february 14th 2024 by admin the rise and fall of philips data systems about a year ago mats danielson from stockholm sweden contacted the cpu shack about an interesting project documenting the history of philips data systems a former powerhouse of european computing previously we wrote about the spc16 micro used in some of these but mats has done a complete history his book is available for free at research gate the rise and fall of philips data systems it includes the spc16 as well as the history of much of swedish computing we re always happy to help out researchers be it with data or just pictures tags philips posted in research december 21st 2023 by admin the first mass produced dram of the soviet union in 1966 american engineer and inventor robert dennard invented dynamic ram cells single transistor cells each bit of information is stored in the form of an electric charge of a capacitor by that time mos technology was already capable of creating capacitors the presence or absence of a charge on a capacitor represents one or zero bits of information and the transistor can control the recording of the charge into the capacitor at the time dennard was working on a six transistor memory cell so he could only devote his spare time to his new idea after figuring out the intricacies of writing charge into a capacitor using a transistor and then reading it back through the same transistor dennard and ibm applied for a patent for single transistor dynamic random access memory robert dennard and his single transistor memory cell however the first commercially available dynamic memory chip the 1103 released by intel in october 1970 used three transistors per cell and separate lines to write and read data a single transistor circuit requires a sophisticated signal amplifier to read the data it was impossible to implement such an amplifier on a chip with the technology available at that time at the end of 1971 the 1103 became the best selling semiconductor chip in the world by 1972 14 of the 18 mainframe manufacturers in the u s europe and japan were using semiconductor memory instead of magnetic core memory the first commercially available computer the hp9800 was designed using the intel 1103 the first truly mass produced dynamic memory chip in the ussr was the 565ru1 a random access ram with a capacity of 4096 bits and a 4096 x 1 organization it is believed that the prototype for the 565ru1 was the 2107a chip released by intel at the turn of 1973 74 there is some similarities in layout to the 2107a but it certainly is not a direct copy the chip is comparable in technical characteristics to analogues tms4060 from texas instruments and mm5280 from national semiconductor therefore the question of which of the chips was chosen for copying remains open the soviet chip like its western counterparts had a three transistor memory cell intel 2107a bad die shot but you can see decoder circuitry on the left and memory cells 3 transistor per cell on the right intel 2104 2107b w multiplexed inputs single transistor cells image courtesy of evilmonkeyz mostek mk4096 the standard 4k multiplexed single cell dram computer history museum it was in this circuitry that it was produced for many years although the same 2107a was replaced within a year after the start of production by the 2107b chip which already had a single transistor memory cell 565ru1 die manufactured in 1981 565ru1 die manufactured in 1985 nearly identical with a chip released four years earlier read more posted in memory september 2nd 2023 by admin sparcs in space the cobham ut700 leon3ft processor uae mars hope mission ir imager powered by leon3ft in the 1990s the esa began a project to develop their own open source easily usable processor for space applications before this the esa had used mainly mil std 1750a processors both american made ones or direct copies their of such as the dynex mas281 a clone of the mcdonnel douglas mdc281 the esa explored many different architectures including the motorola mc88k risc process the mips risc processor and amd 29k risc processor the sparc and somewhat oddly even the national semiconductor ns32k series processors which at the time were fairly powerful and used a fair amount in embedded apps the sparc came out of this as the winner cypress cy7c601 sparc processor the basis for the erc32 at the time the sparc was a pretty widely used processor and was being developed by multiple companies it was defined as an architecture and various companies could implement it how they saw fit in various technologies this is very much how the 1750a architecture was made to be as well considering this the only two really viable architectures that wouldn t at that time have been a sole source item were the mips and the sparc both were used and made by many companies but sparc it was atmel tsc695 erc32 single chip sparc v7 still in production the first implementation was the erc32 released in 1995 a early sparc v7 3 chip implementation typically made on a 0 8u process these were decent but took 3 chips were limited to 20mhz due to memory interface limitations and were not particularly scalable the erc32 did fly to space and was used on the iss as one of the main control computers as well as 10 other missions including the esas atv resupply vehicles for the iss by 1998 the erc32 was shrunk to 0 6u allowing it to be integrated onto a single chip the atmel tsc695 this became the standard esa processor as well as being used by other nations including china israel india and even nasa by the year 2000 the sparc v7 architecture was rather long in the tooth having been originally designed back in the 1980 s the decision was made to upgrade to sparc v8 sparc v8 added integer multiply divide instructions as well as expanded the floating point from 80 bit to 128 bit sparc v8 became the basis for the ieee 1754 1994 standard for what a 32 bit processor must do this was important as it made a very clear definition for software as well esa wanted a processor whose support was very well known and very well defined the sparc v8 implementation became the leon for lion processor these used a 5 stage pipeline fetch decode execute memory write and were made on a 0 35u process delivering around 50mips at 0 5w it used around 100 000 gates on a 30mm2 die and was a fully fault tolerant design unlike the erc32 it was rated to handle 300krad of ionizing radiation without upset atmel at697 leon2 leon2 was a fairly similar deign it moved the mul div instructions into hardware instead of emulating them on leon1 and reduced the feature size down to 0 18u it also added many on chip peripherals such as a pc133 sdram controller with error detection correction as well as a amba bus it took around 0 6w at 100mips though some implementation saw speeds of up to 120mips at 0 3w leon2 saw use on many missions including the camera controller for the venus express mission and the bepicolombo mission to mercury leon2 was designed as a single function processor but in the real world was often being used as a soc system on a chip this led to the development of the leon3 in 2004 it was originally made on a slightly larger process of 0 20u it ran at around 150mips at 0 4w its biggest upgrades were moving from a 5 stage pipeline to a 7 stage pipeline fetch decode register access execute memory exception write as well as supporting multiprocessing in realization of the actual use cases the leon processors were seeing as socs rather then as single processors the leon3 added a large array of peripherals this included spacewire mil std 1553 interfaces ddr ram controllers usb controllers 1g ethernet mac and much more all stuff that originally had to be added on to previous systems was now on chip cobham ut700 fault tolerant sparc v8 leon3ft the entire design was good for 400mhz on a 0 13u process and used around 25 000 gates like the leons before it the leon3 was designed as a synthesizable device you could implement the entire core in your on asic or fpga or buy an fpga off the shelf already programmed as one aeroflex offers this option you could also buy ready made processors implementing it much like any other cpu cobham now known as caes cobham advanced electronic solutions offers the ut700 the ut700 is a 166mhz processor implementing the full leon3ft design the ft stands for fault tolerant and adds a lot of error checking and correcting features on top of the bas...